From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Changhuang Liang <changhuang.liang@starfivetech.com>
Cc: Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <mwalle@kernel.org>,
Takahiro Kuwano <takahiro.kuwano@infineon.com>,
Mark Brown <broonie@kernel.org>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>
Subject: Re: [PATCH v1 1/4] spi: dw: Add DDR (Dual Data-Rate) support for enhanced SPI mode
Date: Fri, 23 Oct 2026 11:52:00 +0200 [thread overview]
Message-ID: <877bj8pwvz.fsf@bootlin.com> (raw)
In-Reply-To: <ZQ4PR01MB1202C6B2531173B2D395C619F2642@ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn> (Changhuang Liang's message of "Fri, 23 Oct 2026 09:42:56 +0000")
>> > --- a/drivers/spi/spi-dw-core.c
>> > +++ b/drivers/spi/spi-dw-core.c
>> > @@ -46,6 +46,8 @@ struct dw_spi_enh_cfg {
>> > u8 inst_l;
>> > u8 addr_l;
>> > u8 trans_t;
>> > + bool inst_ddr;
>> > + bool spi_ddr;
>>
>> If I understand this correctly, spi_ddr is quite a bad name because it means
>> address and dummy and data ddr (but not instr). Can you try to come up with
>> a better name for this variable?
>
> spi_ddr is named exactly that way on the register field. Perhaps I won't change
> this variable name, and just add some comments to this variable—what
> do you think?
This is a boolean, not a register bit field. Please use a name that
makes sense here. This is the part of the software that people must
understanding without deep hardware knowlege. You can keep the hardware
name for naming the bitfield operation if that's relevant though.
>> Also, if my above understanding is correct, you must provide a
>> supports_op() callback which would refuse any xS-xS-xD but allow xD-xD-xD
>> and xS-xD-D modes.
>
> OK, I'll add some filter conditions.
>
> Best Regards,
> Changhuang
next prev parent reply other threads:[~2026-10-23 9:52 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-22 10:26 [PATCH v1 0/4] Add DDR (Dual Data-Rate) support for DW SPI controller Changhuang Liang
2026-10-22 10:26 ` [PATCH v1 1/4] spi: dw: Add DDR (Dual Data-Rate) support for enhanced SPI mode Changhuang Liang
2026-10-22 10:41 ` Miquel Raynal
2026-10-23 9:42 ` Changhuang Liang
2026-10-23 9:52 ` Miquel Raynal [this message]
2026-10-23 9:54 ` Changhuang Liang
2026-10-22 10:26 ` [PATCH v1 2/4] mtd: spi-nor: Support mixed 1S-xD-xD DTR protocols in spi_nor_spimem_setup_op() Changhuang Liang
2026-10-22 10:45 ` Miquel Raynal
2026-10-22 12:19 ` Michael Walle
2026-10-22 13:27 ` Miquel Raynal
2026-10-22 10:26 ` [PATCH v1 3/4] mtd: spi-nor: debugfs: Correct DTR protocol names for 1S-xD-xD modes Changhuang Liang
2026-10-22 10:46 ` Miquel Raynal
2026-10-22 10:26 ` [PATCH v1 4/4] mtd: spi-nor: macronix: Add 1-4-4 DTR read support for MX66L1G45G Changhuang Liang
2026-10-22 10:47 ` Miquel Raynal
2026-10-22 12:23 ` Michael Walle
2026-10-23 10:42 ` Changhuang Liang
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