Re: [PATCH] powerpc/mpc85xx: also write addr_h to spin table for 64bit boot entry

[Michael Ellerman <mpe@ellerman.id.au>]

yingjie_bai@126.com writes:
> From: Bai Yingjie <byj.tea@gmail.com>
>
> CPU like P4080 has 36bit physical address, its DDR physical
> start address can be configured above 4G by LAW registers.
>
> For such systems in which their physical memory start address was
> configured higher than 4G, we need also to write addr_h into the spin
> table of the target secondary CPU, so that addr_h and addr_l together
> represent a 64bit physical address.
> Otherwise the secondary core can not get correct entry to start from.
>
> This should do no harm for normal case where addr_h is all 0.
>
> Signed-off-by: Bai Yingjie <byj.tea@gmail.com>
> ---
>  arch/powerpc/platforms/85xx/smp.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
> index 8c7ea2486bc0..f12cdd1e80ff 100644
> --- a/arch/powerpc/platforms/85xx/smp.c
> +++ b/arch/powerpc/platforms/85xx/smp.c
> @@ -252,6 +252,14 @@ static int smp_85xx_start_cpu(int cpu)
>  	out_be64((u64 *)(&spin_table->addr_h),
>  		__pa(ppc_function_entry(generic_secondary_smp_init)));
>  #else
> +	/*
> +	 * We need also to write addr_h to spin table for systems
> +	 * in which their physical memory start address was configured
> +	 * to above 4G, otherwise the secondary core can not get
> +	 * correct entry to start from.
> +	 * This does no harm for normal case where addr_h is all 0.
> +	 */
> +	out_be32(&spin_table->addr_h, __pa(__early_start) >> 32);
>  	out_be32(&spin_table->addr_l, __pa(__early_start));

This breaks the corenet32_smp_defconfig build:

  /linux/arch/powerpc/platforms/85xx/smp.c: In function 'smp_85xx_start_cpu':
  /linux/arch/powerpc/platforms/85xx/smp.c:262:52: error: right shift count >= width of type [-Werror=shift-count-overflow]
    262 |  out_be32(&spin_table->addr_h, __pa(__early_start) >> 32);
        |                                                    ^~
  cc1: all warnings being treated as errors

cheers