From: Esben Haabendal <esben@geanix.com>
To: "Liu Ying" <victor.liu@nxp.com>
Cc: "Andrzej Hajda" <andrzej.hajda@intel.com>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Robert Foss" <rfoss@kernel.org>,
"Laurent Pinchart" <Laurent.pinchart@ideasonboard.com>,
"Jonas Karlman" <jonas@kwiboo.se>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Luca Ceresoli" <luca.ceresoli@bootlin.com>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Guido Günther" <agx@sigxcpu.org>,
"Fabio Estevam" <festevam@gmail.com>,
"Robert Chiras" <robert.chiras@nxp.com>,
"Sam Ravnborg" <sam@ravnborg.org>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
"Oliver F. Brown" <oliver.brown@oss.nxp.com>
Subject: Re: [PATCH RESEND v4 4/4] drm/bridge: nwl-dsi: Correct MIPI DSI horizontal sync timing
Date: Tue, 27 Oct 2026 11:18:24 +0100 [thread overview]
Message-ID: <87qzhbbg5r.fsf@geanix.com> (raw)
In-Reply-To: <atH4i_KcmccKb8Ge@raspi>
Sorry for the premature send of the previous reply.
"Liu Ying" <victor.liu@nxp.com> writes:
>>
>> diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
>> index f3f4334136c0..eb604733eea0 100644
>> --- a/drivers/gpu/drm/bridge/nwl-dsi.c
>> +++ b/drivers/gpu/drm/bridge/nwl-dsi.c
>> @@ -22,6 +22,7 @@
>> #include <linux/reset.h>
>> #include <linux/sys_soc.h>
>> #include <linux/time64.h>
>> +#include <linux/math64.h>
>
> Sort the header files alphabetically.
Will do.
>> + hfp = roundup(hfp, 2);
>> + hbp = roundup(hbp, 2);
>> + hsa = roundup(hsa, 2);
>> +
>> + /*
>> + * We need to subtract the packet header length: 32
>> + * In order to make sure we don't get negative values,
>> + * subtract a proportional value to the total length of the
>> + * horizontal blanking duration.
>> + */
>> + h_blank = hfp + hbp + hsa;
>> +
>> + if (h_blank) {
>> + pkt_len = min(hfp, roundup(((hfp * 100 / h_blank) * 32) / 100, 2));
>> + pkt_hdr_len = pkt_len;
>> + hfp -= pkt_len;
>> +
>> + pkt_len = min(hbp, roundup(((hbp * 100 / h_blank) * 32) / 100, 2));
>> + pkt_hdr_len += pkt_len;
>> + hbp -= pkt_len;
>> +
>> + pkt_len = min(hsa, 32 - pkt_hdr_len);
>> + pkt_hdr_len += pkt_len;
>> + hsa -= pkt_len;
>> + if (pkt_hdr_len != 32)
>> + dev_warn(dsi->dev,
>> + "Unable to subtract packet header length fully: %d left\n",
>> + 32 - pkt_hdr_len);
>> + }
>> +
>> + DRM_DEV_DEBUG_DRIVER(dsi->dev, "Register values: hfp=%d hbp=%d hsa=%d\n", hfp, hbp, hsa);
>> +
>> + nwl_dsi_write(dsi, NWL_DSI_HFP, hfp);
>> + nwl_dsi_write(dsi, NWL_DSI_HBP, hbp);
>> + nwl_dsi_write(dsi, NWL_DSI_HSA, hsa);
>>
>> nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
>> nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
>>
>> --
>> 2.56.0
>>
>
> Not sure if the fix is 100% correct, but it is a correct direction to
> change the blanking packet payload size from in pixel clocks to in bytes,
> so better than no fix:
> Acked-by: Liu Ying <victor.liu@nxp.com>
Thanks. With the information available to me, this is the best I can do.
/Esben
next prev parent reply other threads:[~2026-10-27 10:18 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-14 7:44 [PATCH RESEND v4 0/4] drm/bridge: nwl-dsi: Various fixes Esben Haabendal
2026-10-14 7:44 ` [PATCH RESEND v4 1/4] drm/bridge: nwl-dsi: Cleanup endpoint mux control selection Esben Haabendal
2026-10-14 7:44 ` [PATCH RESEND v4 2/4] drm/bridge: nwl-dsi: Limit LCDIF specific sync override Esben Haabendal
2026-10-15 13:54 ` Luca Ceresoli
2026-10-14 7:44 ` [PATCH RESEND v4 3/4] drm/bridge: nwl-dsi: Correct auto-insert EOTP behavior Esben Haabendal
2026-10-15 13:54 ` Luca Ceresoli
2026-10-14 7:44 ` [PATCH RESEND v4 4/4] drm/bridge: nwl-dsi: Correct MIPI DSI horizontal sync timing Esben Haabendal
2026-10-15 13:54 ` Luca Ceresoli
2026-10-15 15:18 ` Frank Li
2026-10-16 10:12 ` Liu Ying
2026-10-27 10:14 ` Esben Haabendal
2026-10-27 10:18 ` Esben Haabendal [this message]
2026-10-25 6:55 ` Sebastian Krzyszkowiak
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