Re: [PATCH RESEND v4 4/4] drm/bridge: nwl-dsi: Correct MIPI DSI horizontal sync timing

[Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>]

On środa, 14 października 2026 09:44:45 czas środkowoeuropejski standardowy 
Esben Haabendal wrote:
> The NWL MIPI Host controller registers specifies the horizontal front
> porch, sync pulse, and back porch in DSI packet payload size in bytes (ie.
> not in pixel clocks).
> 
> The calculation for this is (mostly) described in section 13.6.3.5.1.2 of
> the i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference
> Manual (rev. 3.1). The formula shown there does not take packet header size
> into account though.
> 
> The formula implemented here converts the hfp, hsa, and hbp to DSI packet
> bytes and then subtracts the number of packet header bytes.
> 
> It is worth noting that these values only needs to match approximately,
> according to the reference manual.
> 
> Based on commit in NXP vendor tree
> commit f2a61699749d ("LF-7981-4: drm/bridge: nwl-dsi: Correct MIPI DSI
> horizontal sync timing")
> 
> Signed-off-by: Esben Haabendal <esben@geanix.com>
> Cc: Robert Chiras <robert.chiras@nxp.com>
> Cc: Oliver F. Brown <oliver.brown@oss.nxp.com>

This lets the Librem 5 screen be driven without additional timing hacks.

Tested-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>