Re: [PATCH v2 1/2] drm/radeon: process the VCE interrupt on SI and Trinity

["Christian König" <christian.koenig@amd.com>]

On 10/22/26 13:47, Matheus Tagliari wrote:
> radeon_vce_fence_emit() ends every VCE fence with VCE_CMD_TRAP, which
> raises the VCE trap interrupt (IH src_id 167).  cik_irq_process()
> handles it by calling radeon_fence_process() for the matching VCE ring,
> but si_irq_process() and evergreen_irq_process(), which serve the other
> ASICs with VCE1 (SI and Trinity/Richland), have no case for it.
> 
> Add the same handling.  The trap interrupt is not enabled on these
> ASICs yet, so this does not change behaviour on its own; the next patch
> enables it.
> 
> The SI part was tested together with the next patch.  The Trinity part
> mirrors the CIK and SI code and has not been tested on Trinity/Richland
> hardware.
> 
> Fixes: a918efab631a ("drm/radeon: add VCE 1.0 support v4")
> Cc: stable@vger.kernel.org

Please drop that, we really don't want this to be backported.

> Signed-off-by: Matheus Tagliari <mptagliari@gmail.com>

With the CC: stable tag dropped Acked-by: Christian König <christian.koenig@amd.com>

> ---
>  drivers/gpu/drm/radeon/evergreen.c | 14 ++++++++++++++
>  drivers/gpu/drm/radeon/si.c        | 14 ++++++++++++++
>  2 files changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
> index 3cbc6eedb..eb94916c8 100644
> --- a/drivers/gpu/drm/radeon/evergreen.c
> +++ b/drivers/gpu/drm/radeon/evergreen.c
> @@ -4847,6 +4847,20 @@ int evergreen_irq_process(struct radeon_device *rdev)
>  			drm_dbg(ddev, "IH: UVD int: 0x%08x\n", src_data);
>  			radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
>  			break;
> +		case 167: /* VCE */
> +			drm_dbg(ddev, "IH: VCE int: 0x%08x\n", src_data);
> +			switch (src_data) {
> +			case 0:
> +				radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX);
> +				break;
> +			case 1:
> +				radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX);
> +				break;
> +			default:
> +				drm_err(ddev, "Unhandled interrupt: %d %d\n", src_id, src_data);
> +				break;
> +			}
> +			break;
>  		case 146:
>  		case 147:
>  			addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index 4681ff286..af3c4026d 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -6347,6 +6347,20 @@ int si_irq_process(struct radeon_device *rdev)
>  			DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
>  			radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
>  			break;
> +		case 167: /* VCE */
> +			DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
> +			switch (src_data) {
> +			case 0:
> +				radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX);
> +				break;
> +			case 1:
> +				radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX);
> +				break;
> +			default:
> +				DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
> +				break;
> +			}
> +			break;
>  		case 146:
>  		case 147:
>  			addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);