[PATCH] drm/mediatek: mtk_dsi: Enable HS clock only at pre-enable

[PATCH] drm/mediatek: mtk_dsi: Enable HS clock only at pre-enable

[AngeloGioacchino Del Regno]

Commit 76255024cadb ("drm/mediatek: mtk_dsi: enable hs clock
during pre-enable") rightfully moves the HS clock enablement to
before atomic_enable(), but it's moving it to mtk_dsi_poweron(),
which is not only called in the .atomic_pre_enable() callback
for the DRM bridge, but also in the MediaTek DRM's .ddp_start()
callback, which happens way before the bridge ones.

The HS clock enablement should be done at just the right time,
otherwise some bridge chips (or some Display Driver ICs) may
not work correctly: this is seen at least with a Parade DSI to
eDP bridge (PS8640) on the MT8173 Elm Chromebook.

This resolves a regression that was seen on the aforementioned
machine, which was happening only after a suspend-resume cycle.

Cc: <stable@vger.kernel.org> # 7.1.x
Fixes: 76255024cadb ("drm/mediatek: mtk_dsi: enable hs clock during pre-enable")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index dc0c4e867179..c729a163bda6 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1165,8 +1165,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 		goto err_disable_dsi_and_digital_clk;
 
 	mtk_dsi_set_interrupt_enable(dsi);
-	mtk_dsi_lane_ready(dsi);
-	mtk_dsi_clk_hs_mode(dsi, 1);
 
 	return 0;
 
@@ -1284,6 +1282,9 @@ static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
 	ret = mtk_dsi_poweron(dsi);
 	if (ret < 0)
 		drm_err(drm, "failed to power on dsi\n");
+
+	mtk_dsi_lane_ready(dsi);
+	mtk_dsi_clk_hs_mode(dsi, 1);
 }
 
 static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,
-- 
2.55.0

Re: [PATCH] drm/mediatek: mtk_dsi: Enable HS clock only at pre-enable

[Adam Thiede]

On 7/28/26 10:31, AngeloGioacchino Del Regno wrote:
> Commit 76255024cadb ("drm/mediatek: mtk_dsi: enable hs clock
> during pre-enable") rightfully moves the HS clock enablement to
> before atomic_enable(), but it's moving it to mtk_dsi_poweron(),
> which is not only called in the .atomic_pre_enable() callback
> for the DRM bridge, but also in the MediaTek DRM's .ddp_start()
> callback, which happens way before the bridge ones.
> 
> The HS clock enablement should be done at just the right time,
> otherwise some bridge chips (or some Display Driver ICs) may
> not work correctly: this is seen at least with a Parade DSI to
> eDP bridge (PS8640) on the MT8173 Elm Chromebook.
> 
> This resolves a regression that was seen on the aforementioned
> machine, which was happening only after a suspend-resume cycle.
> 
> Cc: <stable@vger.kernel.org> # 7.1.x
> Fixes: 76255024cadb ("drm/mediatek: mtk_dsi: enable hs clock during pre-enable")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   drivers/gpu/drm/mediatek/mtk_dsi.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index dc0c4e867179..c729a163bda6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -1165,8 +1165,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
>   		goto err_disable_dsi_and_digital_clk;
>   
>   	mtk_dsi_set_interrupt_enable(dsi);
> -	mtk_dsi_lane_ready(dsi);
> -	mtk_dsi_clk_hs_mode(dsi, 1);
>   
>   	return 0;
>   
> @@ -1284,6 +1282,9 @@ static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
>   	ret = mtk_dsi_poweron(dsi);
>   	if (ret < 0)
>   		drm_err(drm, "failed to power on dsi\n");
> +
> +	mtk_dsi_lane_ready(dsi);
> +	mtk_dsi_clk_hs_mode(dsi, 1);
>   }
>   
>   static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,

Tested-by: Adam Thiede <me@adamthiede.com>

Re: [PATCH] drm/mediatek: mtk_dsi: Enable HS clock only at pre-enable

[CK Hu (胡俊光)]

On Tue, 2026-07-28 at 17:31 +0200, AngeloGioacchino Del Regno wrote:
> Commit 76255024cadb ("drm/mediatek: mtk_dsi: enable hs clock
> during pre-enable") rightfully moves the HS clock enablement to
> before atomic_enable(), but it's moving it to mtk_dsi_poweron(),
> which is not only called in the .atomic_pre_enable() callback
> for the DRM bridge, but also in the MediaTek DRM's .ddp_start()
> callback, which happens way before the bridge ones.
> 
> The HS clock enablement should be done at just the right time,
> otherwise some bridge chips (or some Display Driver ICs) may
> not work correctly: this is seen at least with a Parade DSI to
> eDP bridge (PS8640) on the MT8173 Elm Chromebook.
> 
> This resolves a regression that was seen on the aforementioned
> machine, which was happening only after a suspend-resume cycle.

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Cc: <stable@vger.kernel.org> # 7.1.x
> Fixes: 76255024cadb ("drm/mediatek: mtk_dsi: enable hs clock during pre-enable")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---