[PATCH 25/40] nitro_enclaves: Read the interrupt multiplexer geometry at probe

[Alexander Graf <graf@amazon.com>]

In preparation to support per-virtqueue events for Nitro Sandboxes, read
the geometry of the interrupt multiplexer at probe. The interrupt
multiplexer is built into the nitro_enclaves device. It is a pool of
MSI-X vectors that the device shares between the virtqueues of every
sandbox: it raises a pooled vector and records in a bitmap which queues
signalled. NE_MUX_NUM_VECTORS holds the size of the pool and
NE_MUX_VECTOR_BASE its first vector.

Read them only on a device with the PCI vendor-specific capability that
defines them. Leave the pool unused when it is larger than
NE_MUX_MAX_VECTORS or than the vectors of the device, or when it
overlaps the reply and event vectors.

Signed-off-by: Alexander Graf <graf@amazon.com>
---
 drivers/virt/nitro_enclaves/ne_pci_dev.c | 60 ++++++++++++++++++++++--
 drivers/virt/nitro_enclaves/ne_pci_dev.h | 27 ++++++++++-
 2 files changed, 81 insertions(+), 6 deletions(-)

diff --git a/drivers/virt/nitro_enclaves/ne_pci_dev.c b/drivers/virt/nitro_enclaves/ne_pci_dev.c
index 1aa4d5508dabf..05dd3040afbc3 100644
--- a/drivers/virt/nitro_enclaves/ne_pci_dev.c
+++ b/drivers/virt/nitro_enclaves/ne_pci_dev.c
@@ -550,6 +550,55 @@ static void ne_teardown_msix(struct pci_dev *pdev)
 	pci_free_irq_vectors(pdev);
 }
 
+/**
+ * ne_mux_setup() - Read the interrupt multiplexer geometry from the device.
+ * @pdev:	PCI device to read the multiplexer geometry of.
+ *
+ * The multiplexer registers only exist on a device that publishes a
+ * vendor-specific capability, so a device without one leaves the pool unused
+ * and reads no multiplexer register at all.
+ *
+ * Context: Process context.
+ * Return:
+ * * 0 on success.
+ */
+static int ne_mux_setup(struct pci_dev *pdev)
+{
+	struct ne_pci_dev *ne_pci_dev = pci_get_drvdata(pdev);
+	int msix_nr_vecs = 0;
+	u32 nr_vecs = 0;
+	u32 vec_base = 0;
+
+	if (!ne_pci_dev->has_vendor_cap)
+		return 0;
+
+	nr_vecs = ioread16(ne_pci_dev->iomem_base + NE_MUX_NUM_VECTORS);
+	if (!nr_vecs)
+		return 0;
+
+	vec_base = ioread16(ne_pci_dev->iomem_base + NE_MUX_VECTOR_BASE);
+	msix_nr_vecs = pci_msix_vec_count(pdev);
+
+	/*
+	 * An enclave whose queues cannot reach the pool binds them to the
+	 * reply and event vectors instead, which costs interrupt throughput
+	 * and no functionality. Refusing to probe would take Nitro Enclaves
+	 * away from the parent altogether.
+	 */
+	if (nr_vecs > NE_MUX_MAX_VECTORS || vec_base <= NE_VEC_EVENT ||
+	    msix_nr_vecs < 0 || vec_base + nr_vecs > (u32)msix_nr_vecs) {
+		dev_dbg(&pdev->dev, "Unusable multiplexer pool of %u vectors at vector %u\n",
+			nr_vecs, vec_base);
+
+		return 0;
+	}
+
+	ne_pci_dev->mux_nr_vecs = nr_vecs;
+	ne_pci_dev->mux_vec_base = vec_base;
+
+	return 0;
+}
+
 /**
  * ne_pci_dev_enable() - Select the PCI device version and enable it.
  * @pdev:	PCI device to select version for and then enable.
@@ -1574,10 +1623,11 @@ static int ne_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	ne_pci_dev->pdev = pdev;
 
 	/*
-	 * The registers past the command interface only exist on a device that
-	 * publishes a vendor-specific capability, and a read of a register the
-	 * device does not implement has no defined value. The answer holds for
-	 * the life of the device, so look it up once here.
+	 * Launch flags, the multiplexer and the slot pool registers are
+	 * implemented by a device that publishes a vendor-specific capability,
+	 * and a read of a register the device does not implement has no defined
+	 * value. The answer holds
+	 * for the life of the device, so look it up once here.
 	 */
 	ne_pci_dev->has_vendor_cap =
 		pci_find_capability(pdev, PCI_CAP_ID_VNDR) != 0;
@@ -1598,6 +1648,8 @@ static int ne_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 		goto teardown_msix;
 	}
 
+	ne_mux_setup(pdev);
+
 	down_write(&ne_devs.lock);
 
 	/*
diff --git a/drivers/virt/nitro_enclaves/ne_pci_dev.h b/drivers/virt/nitro_enclaves/ne_pci_dev.h
index a0bca5863e2a1..aee22b4ed8b6e 100644
--- a/drivers/virt/nitro_enclaves/ne_pci_dev.h
+++ b/drivers/virt/nitro_enclaves/ne_pci_dev.h
@@ -54,6 +54,12 @@
  */
 #define NE_COMMAND		(0x0004)
 
+/**
+ * NE_MUX_VECTOR_BASE - (2 bytes) Register holding the first MSI-X vector of
+ *			the interrupt multiplexer pool (Read-Only).
+ */
+#define NE_MUX_VECTOR_BASE	(0x0008)
+
 /**
  * NE_EVTCNT - (4 bytes) Register to notify the driver that a reply or a device
  *	       event is available (Read-Only):
@@ -82,6 +88,12 @@
  */
 #define NE_RECV_DATA		(0x0100)
 
+/**
+ * NE_MUX_NUM_VECTORS - (2 bytes) Register holding the number of MSI-X vectors
+ *			in the interrupt multiplexer pool (Read-Only).
+ */
+#define NE_MUX_NUM_VECTORS	(0x01f0)
+
 /**
  * DOC: Device MMIO buffer sizes
  */
@@ -146,6 +158,11 @@
  */
 #define NE_VEC_EVENT		(1)
 
+/**
+ * NE_MUX_MAX_VECTORS - Largest interrupt multiplexer pool the driver accepts.
+ */
+#define NE_MUX_MAX_VECTORS	(256)
+
 /**
  * enum ne_pci_dev_cmd_type - Device command types.
  * @INVALID_CMD:		Invalid command.
@@ -604,9 +621,13 @@ struct ne_slot_pool_run {
  *				enclave state scanning and propagation to the
  *				enclave process.
  * @has_vendor_cap:		Whether the PCI device publishes a vendor-specific
- *				capability, and with it the registers past the
- *				command interface.
+ *				capability, and with it the multiplexer and slot
+ *				pool registers.
  * @iomem_base :		MMIO region of the PCI device.
+ * @mux_nr_vecs:		Number of MSI-X vectors in the interrupt
+ *				multiplexer pool.
+ * @mux_vec_base:		First MSI-X vector of the interrupt multiplexer
+ *				pool.
  * @notify_work:		Work item for every received out-of-band event.
  * @pci_dev_mutex:		Mutex for accessing the PCI device MMIO space.
  * @pdev:			PCI device data structure.
@@ -636,6 +657,8 @@ struct ne_pci_dev {
 	struct workqueue_struct	*event_wq;
 	bool			has_vendor_cap;
 	void __iomem		*iomem_base;
+	u32			mux_nr_vecs;
+	u32			mux_vec_base;
 	struct work_struct	notify_work;
 	struct mutex		pci_dev_mutex;
 	struct pci_dev		*pdev;
-- 
2.47.1