From: Dinh Nguyen <dinguyen@kernel.org>
To: p.zabel@pengutronix.de
Cc: linux-kernel@vger.kernel.org
Subject: Re: [PATCH] reset: socfpga: fix for 64-bit compilation
Date: Mon, 2 Oct 2017 16:36:46 -0500 [thread overview]
Message-ID: <8d03d14e-5c31-e01a-bfe6-7ac17112e258@kernel.org> (raw)
In-Reply-To: <1506105767-15889-1-git-send-email-dinguyen@kernel.org>
Gentle ping?
Dinh
On 09/22/2017 01:42 PM, Dinh Nguyen wrote:
> The SoCFPGA Stratix10 reset controller has 32-bit registers. Thus, we
> cannot use BITS_PER_LONG in computing the register and bit offset. Instead,
> we should be using the width of the hardware register for the calculation.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> drivers/reset/reset-socfpga.c | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
> index c60904f..3907bbc 100644
> --- a/drivers/reset/reset-socfpga.c
> +++ b/drivers/reset/reset-socfpga.c
> @@ -40,8 +40,9 @@ static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
> struct socfpga_reset_data *data = container_of(rcdev,
> struct socfpga_reset_data,
> rcdev);
> - int bank = id / BITS_PER_LONG;
> - int offset = id % BITS_PER_LONG;
> + int reg_width = sizeof(u32);
> + int bank = id / (reg_width * BITS_PER_BYTE);
> + int offset = id % (reg_width * BITS_PER_BYTE);
> unsigned long flags;
> u32 reg;
>
> @@ -61,8 +62,9 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
> struct socfpga_reset_data,
> rcdev);
>
> - int bank = id / BITS_PER_LONG;
> - int offset = id % BITS_PER_LONG;
> + int reg_width = sizeof(u32);
> + int bank = id / (reg_width * BITS_PER_BYTE);
> + int offset = id % (reg_width * BITS_PER_BYTE);
> unsigned long flags;
> u32 reg;
>
> @@ -81,8 +83,9 @@ static int socfpga_reset_status(struct reset_controller_dev *rcdev,
> {
> struct socfpga_reset_data *data = container_of(rcdev,
> struct socfpga_reset_data, rcdev);
> - int bank = id / BITS_PER_LONG;
> - int offset = id % BITS_PER_LONG;
> + int reg_width = sizeof(u32);
> + int bank = id / (reg_width * BITS_PER_BYTE);
> + int offset = id % (reg_width * BITS_PER_BYTE);
> u32 reg;
>
> reg = readl(data->membase + (bank * BANK_INCREMENT));
> @@ -132,7 +135,7 @@ static int socfpga_reset_probe(struct platform_device *pdev)
> spin_lock_init(&data->lock);
>
> data->rcdev.owner = THIS_MODULE;
> - data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
> + data->rcdev.nr_resets = NR_BANKS * (sizeof(u32) * BITS_PER_BYTE);
> data->rcdev.ops = &socfpga_reset_ops;
> data->rcdev.of_node = pdev->dev.of_node;
>
>
next prev parent reply other threads:[~2017-10-02 21:36 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-22 18:42 Dinh Nguyen
2017-10-02 21:36 ` Dinh Nguyen [this message]
2017-10-04 9:27 ` Philipp Zabel
2017-10-04 12:41 ` Dinh Nguyen
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