* [PATCH] mtd: spi-nor: add support for GD25Q256
@ 2017-02-14 0:36 Andy Yan
2017-02-14 4:44 ` Marek Vasut
2017-02-14 10:35 ` Cyrille Pitchen
0 siblings, 2 replies; 3+ messages in thread
From: Andy Yan @ 2017-02-14 0:36 UTC (permalink / raw)
To: cyrille.pitchen, marek.vasut
Cc: dwmw2, computersforpeace, boris.brezillon, richard, linux-mtd,
linux-kernel, Andy Yan
GD25Q256 is a 32MiB SPI Nor flash from Gigadevice.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
drivers/mtd/spi-nor/spi-nor.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
mode change 100644 => 100755 drivers/mtd/spi-nor/spi-nor.c
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
old mode 100644
new mode 100755
index da7cd69..0917dd3
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -852,6 +852,10 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ },
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
@@ -1483,7 +1487,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
else if (mtd->size > 0x1000000) {
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;
- if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
+ JEDEC_MFR(info) == SNOR_MFR_GIGADEVICE) {
/* Dedicated 4-byte command set */
switch (nor->flash_read) {
case SPI_NOR_QUAD:
@@ -1519,7 +1524,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
dev_info(dev, "%s (%lld Kbytes)\n", info->name,
(long long)mtd->size >> 10);
-
dev_dbg(dev,
"mtd .name = %s, .size = 0x%llx (%lldMiB), "
".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
--
2.7.4
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] mtd: spi-nor: add support for GD25Q256
2017-02-14 0:36 [PATCH] mtd: spi-nor: add support for GD25Q256 Andy Yan
@ 2017-02-14 4:44 ` Marek Vasut
2017-02-14 10:35 ` Cyrille Pitchen
1 sibling, 0 replies; 3+ messages in thread
From: Marek Vasut @ 2017-02-14 4:44 UTC (permalink / raw)
To: Andy Yan, cyrille.pitchen
Cc: dwmw2, computersforpeace, boris.brezillon, richard, linux-mtd,
linux-kernel
On 02/14/2017 01:36 AM, Andy Yan wrote:
> GD25Q256 is a 32MiB SPI Nor flash from Gigadevice.
That's great, and what is this patch doing with it ? Adding support for
it, right? Then it should be in the commit message.
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
> mode change 100644 => 100755 drivers/mtd/spi-nor/spi-nor.c
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> old mode 100644
> new mode 100755
> index da7cd69..0917dd3
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -852,6 +852,10 @@ static const struct flash_info spi_nor_ids[] = {
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> },
> + {
> + "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
> + },
>
> /* Intel/Numonyx -- xxxs33b */
> { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
> @@ -1483,7 +1487,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
> else if (mtd->size > 0x1000000) {
> /* enable 4-byte addressing if the device exceeds 16MiB */
> nor->addr_width = 4;
> - if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
> + if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
> + JEDEC_MFR(info) == SNOR_MFR_GIGADEVICE) {
> /* Dedicated 4-byte command set */
> switch (nor->flash_read) {
> case SPI_NOR_QUAD:
> @@ -1519,7 +1524,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
>
> dev_info(dev, "%s (%lld Kbytes)\n", info->name,
> (long long)mtd->size >> 10);
> -
Drop this one new line.
> dev_dbg(dev,
> "mtd .name = %s, .size = 0x%llx (%lldMiB), "
> ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] mtd: spi-nor: add support for GD25Q256
2017-02-14 0:36 [PATCH] mtd: spi-nor: add support for GD25Q256 Andy Yan
2017-02-14 4:44 ` Marek Vasut
@ 2017-02-14 10:35 ` Cyrille Pitchen
1 sibling, 0 replies; 3+ messages in thread
From: Cyrille Pitchen @ 2017-02-14 10:35 UTC (permalink / raw)
To: Andy Yan, marek.vasut
Cc: dwmw2, computersforpeace, boris.brezillon, richard, linux-mtd,
linux-kernel
Hi Andy,
Le 14/02/2017 à 01:36, Andy Yan a écrit :
> GD25Q256 is a 32MiB SPI Nor flash from Gigadevice.
>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
> mode change 100644 => 100755 drivers/mtd/spi-nor/spi-nor.c
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> old mode 100644
> new mode 100755
> index da7cd69..0917dd3
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -852,6 +852,10 @@ static const struct flash_info spi_nor_ids[] = {
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> },
> + {
> + "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
> + },
>
> /* Intel/Numonyx -- xxxs33b */
> { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
> @@ -1483,7 +1487,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
> else if (mtd->size > 0x1000000) {
> /* enable 4-byte addressing if the device exceeds 16MiB */
> nor->addr_width = 4;
> - if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
> + if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
> + JEDEC_MFR(info) == SNOR_MFR_GIGADEVICE) {
> /* Dedicated 4-byte command set */
> switch (nor->flash_read) {
> case SPI_NOR_QUAD:
This doesn't apply to the spi-nor tree and also, please use the
SPI_NOR_4B_OPCODES info->flags instead of adding a "JEDEC_MFR(info) ==
SNOR_MFR_GIGADEVICE" line.
I think setting flags at the memory part level is safer than applying a
global policy per manufacturer.
Best regards,
Cyrille
> @@ -1519,7 +1524,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
>
> dev_info(dev, "%s (%lld Kbytes)\n", info->name,
> (long long)mtd->size >> 10);
> -
> dev_dbg(dev,
> "mtd .name = %s, .size = 0x%llx (%lldMiB), "
> ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2017-02-14 10:35 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-14 0:36 [PATCH] mtd: spi-nor: add support for GD25Q256 Andy Yan
2017-02-14 4:44 ` Marek Vasut
2017-02-14 10:35 ` Cyrille Pitchen
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®