Re: [PATCH 4/5] ARM: dts: zynq: Use dynamic CoreSight funnel and trim clocks

[Michal Simek <michal.simek@amd.com>]

On 10/2/26 17:07, Leo Yan wrote:
> The Zynq-7000 funnel at 0xf8804000 has input-enable registers.
> Describe it as a dynamic funnel so the CoreSight driver programs
> them. Keep the existing apb_pclk reference required by AMBA probing.
> 
> The static replicator has no programming registers, so remove its
> clock references. CoreSight drivers do not request dbg_trc or dbg_apb
> for the funnel, ETB, TPIU or PTMs. Drop those references while keeping
> apb_pclk for the programmable AMBA devices.
> 
> The Zynq clock controller registers dbg_trc and dbg_apb and calls
> clk_prepare_enable() for each gate the bootloader left on (see
> zynq_clk_setup()). This does not depend on the CoreSight nodes' clock
> references, so removing the unused consumer entries leaves this
> protection intact.
> 
> Assisted-by: Codex:gpt-6
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
>   arch/arm/boot/dts/xilinx/zynq-7000.dtsi | 24 +++++++++++-------------
>   1 file changed, 11 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/xilinx/zynq-7000.dtsi b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi
> index 153b8d93cbee2c30b399c0770f2022b307fe0808..4280fe6da379064b6ac5bf9e9a5b891830a094b2 100644
> --- a/arch/arm/boot/dts/xilinx/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi
> @@ -68,8 +68,6 @@ regulator_vccpint: fixedregulator {
>   
>   	replicator {
>   		compatible = "arm,coresight-static-replicator";
> -		clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> -		clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>   
>   		out-ports {
>   			#address-cells = <1>;
> @@ -464,8 +462,8 @@ watchdog0: watchdog@f8005000 {
>   		etb@f8801000 {
>   			compatible = "arm,coresight-etb10", "arm,primecell";
>   			reg = <0xf8801000 0x1000>;
> -			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> -			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +			clocks = <&clkc 27>;
> +			clock-names = "apb_pclk";
>   			in-ports {
>   				port {
>   					etb_in_port: endpoint {
> @@ -478,8 +476,8 @@ etb_in_port: endpoint {
>   		tpiu@f8803000 {
>   			compatible = "arm,coresight-tpiu", "arm,primecell";
>   			reg = <0xf8803000 0x1000>;
> -			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> -			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +			clocks = <&clkc 27>;
> +			clock-names = "apb_pclk";
>   			in-ports {
>   				port {
>   					tpiu_in_port: endpoint {
> @@ -490,10 +488,10 @@ tpiu_in_port: endpoint {
>   		};
>   
>   		funnel@f8804000 {
> -			compatible = "arm,coresight-static-funnel", "arm,primecell";
> +			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>   			reg = <0xf8804000 0x1000>;
> -			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> -			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +			clocks = <&clkc 27>;
> +			clock-names = "apb_pclk";
>   
>   			/* funnel output ports */
>   			out-ports {
> @@ -536,8 +534,8 @@ funnel0_in_port2: endpoint {
>   		ptm@f889c000 {
>   			compatible = "arm,coresight-etm3x", "arm,primecell";
>   			reg = <0xf889c000 0x1000>;
> -			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> -			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +			clocks = <&clkc 27>;
> +			clock-names = "apb_pclk";
>   			cpu = <&cpu0>;
>   			out-ports {
>   				port {
> @@ -551,8 +549,8 @@ ptm0_out_port: endpoint {
>   		ptm@f889d000 {
>   			compatible = "arm,coresight-etm3x", "arm,primecell";
>   			reg = <0xf889d000 0x1000>;
> -			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> -			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +			clocks = <&clkc 27>;
> +			clock-names = "apb_pclk";
>   			cpu = <&cpu1>;
>   			out-ports {
>   				port {
> 

Look at my reply in 1/5 and NACK for this. Clock 46/47 needs to be handled and 
described in DT. It means removing them make no sense.

Thanks,
Michal