* [PATCH] mmc: sdhci-pci-gli: Add Genesys Logic GL9768 support
@ 2026-11-03 10:16 Ben Chuang
2026-11-05 6:18 ` Adrian Hunter
0 siblings, 1 reply; 2+ messages in thread
From: Ben Chuang @ 2026-11-03 10:16 UTC (permalink / raw)
To: adrian.hunter, ulfh
Cc: SeanHY.Chen, boris.chen, HL.Liu, benchuanggli, ben.chuang,
linux-mmc, linux-kernel
From: Ben Chuang <ben.chuang@genesyslogic.com.tw>
The GL9768 is the successor to the GL9767 and uses a compatible
register layout. Reuse the GL9767 driver for the GL9768 by adding
the GL9768 PCI device ID to the device ID table.
Clear bits 2 and 3 in the SD Express control register at offset
0x940 when the driver initializes the device. This clears both
bits to zero, matching the GL9767 default configuration.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
---
drivers/mmc/host/sdhci-pci-core.c | 1 +
drivers/mmc/host/sdhci-pci-gli.c | 7 +++++++
drivers/mmc/host/sdhci-pci.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
index a9000f3bd419..db0417238131 100644
--- a/drivers/mmc/host/sdhci-pci-core.c
+++ b/drivers/mmc/host/sdhci-pci-core.c
@@ -1959,6 +1959,7 @@ static const struct pci_device_id pci_ids[] = {
SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
SDHCI_PCI_DEVICE(GLI, 9767, gl9767),
+ SDHCI_PCI_DEVICE(GLI, 9768, gl9767),
SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
/* Generic SD host controller */
{PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index b55618566d65..66452ed8cd8a 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -245,6 +245,8 @@
#define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940
#define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0)
#define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1)
+#define PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_1 BIT(2)
+#define PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_2 BIT(3)
#define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944
#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 BIT(5)
@@ -1354,6 +1356,11 @@ static void gl9767_hw_setting(struct sdhci_pci_slot *slot)
PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF;
pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value);
+ pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
+ value &= ~(PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_1 |
+ PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_2);
+ pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
+
gl9767_vhs_read(pdev);
}
diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h
index f38f0bd4165c..bcae29f8d8da 100644
--- a/drivers/mmc/host/sdhci-pci.h
+++ b/drivers/mmc/host/sdhci-pci.h
@@ -81,6 +81,7 @@
#define PCI_DEVICE_ID_GLI_9750 0x9750
#define PCI_DEVICE_ID_GLI_9763E 0xe763
#define PCI_DEVICE_ID_GLI_9767 0x9767
+#define PCI_DEVICE_ID_GLI_9768 0x9768
/*
* PCI device class and mask
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
--
2.56.0
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] mmc: sdhci-pci-gli: Add Genesys Logic GL9768 support
2026-11-03 10:16 [PATCH] mmc: sdhci-pci-gli: Add Genesys Logic GL9768 support Ben Chuang
@ 2026-11-05 6:18 ` Adrian Hunter
0 siblings, 0 replies; 2+ messages in thread
From: Adrian Hunter @ 2026-11-05 6:18 UTC (permalink / raw)
To: Ben Chuang, ulfh
Cc: SeanHY.Chen, boris.chen, HL.Liu, ben.chuang, linux-mmc, linux-kernel
On 03/11/2026 12:16, Ben Chuang wrote:
> From: Ben Chuang <ben.chuang@genesyslogic.com.tw>
>
> The GL9768 is the successor to the GL9767 and uses a compatible
> register layout. Reuse the GL9767 driver for the GL9768 by adding
> the GL9768 PCI device ID to the device ID table.
>
> Clear bits 2 and 3 in the SD Express control register at offset
> 0x940 when the driver initializes the device. This clears both
> bits to zero, matching the GL9767 default configuration.
>
> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> drivers/mmc/host/sdhci-pci-core.c | 1 +
> drivers/mmc/host/sdhci-pci-gli.c | 7 +++++++
> drivers/mmc/host/sdhci-pci.h | 1 +
> 3 files changed, 9 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
> index a9000f3bd419..db0417238131 100644
> --- a/drivers/mmc/host/sdhci-pci-core.c
> +++ b/drivers/mmc/host/sdhci-pci-core.c
> @@ -1959,6 +1959,7 @@ static const struct pci_device_id pci_ids[] = {
> SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
> SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
> SDHCI_PCI_DEVICE(GLI, 9767, gl9767),
> + SDHCI_PCI_DEVICE(GLI, 9768, gl9767),
> SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
> /* Generic SD host controller */
> {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index b55618566d65..66452ed8cd8a 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -245,6 +245,8 @@
> #define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940
> #define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0)
> #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1)
> +#define PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_1 BIT(2)
> +#define PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_2 BIT(3)
>
> #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944
> #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 BIT(5)
> @@ -1354,6 +1356,11 @@ static void gl9767_hw_setting(struct sdhci_pci_slot *slot)
> PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF;
> pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value);
>
> + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
> + value &= ~(PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_1 |
> + PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_2);
> + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
> +
> gl9767_vhs_read(pdev);
> }
>
> diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h
> index f38f0bd4165c..bcae29f8d8da 100644
> --- a/drivers/mmc/host/sdhci-pci.h
> +++ b/drivers/mmc/host/sdhci-pci.h
> @@ -81,6 +81,7 @@
> #define PCI_DEVICE_ID_GLI_9750 0x9750
> #define PCI_DEVICE_ID_GLI_9763E 0xe763
> #define PCI_DEVICE_ID_GLI_9767 0x9767
> +#define PCI_DEVICE_ID_GLI_9768 0x9768
>
> /*
> * PCI device class and mask
>
> base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
^ permalink raw reply [flat|nested] 2+ messages in thread
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2026-11-05 6:18 ` Adrian Hunter
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