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From: Reinette Chatre <reinette.chatre@intel.com>
To: Xiaochen Shen <shenxiaochen@open-hieco.net>,
	"Luck, Tony" <tony.luck@intel.com>, "bp@alien8.de" <bp@alien8.de>,
	"fenghuay@nvidia.com" <fenghuay@nvidia.com>
Cc: "babu.moger@amd.com" <babu.moger@amd.com>,
	"james.morse@arm.com" <james.morse@arm.com>,
	"Dave.Martin@arm.com" <Dave.Martin@arm.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] x86/resctrl: Fix memory bandwidth counter width for Hygon
Date: Fri, 5 Dec 2025 13:57:41 -0800	[thread overview]
Message-ID: <99e33a39-f0ec-488b-88d9-634158aec6e1@intel.com> (raw)
In-Reply-To: <03618cf2-b8c8-4493-a991-04bced42c7dd@open-hieco.net>

Hi Xiaochen,

On 12/4/25 6:38 PM, Xiaochen Shen wrote:
> Hi Tony,
> 
> On 12/5/2025 1:11 AM, Luck, Tony wrote:
>> I *think* you'd get the right results if the h/w counter is wider
>> than s/w expects. You'd just need to keep polling fast enough
>> (and we never adjusted the MBM polling rate from the original
>> 1 HZ.)
> 
> Thank you very much for code review!
> 
> We have observed a test case where an incorrect counter width leads to random unexpected memory bandwidth readings:
> https://github.com/shenxiaochen/my_documents/blob/main/memory_bandwidth_counter_width_and_overflow_issue_steps_to_reproduce.txt

Could this perhaps be related to issue fixed by:
15292f1b4c55 ("x86/resctrl: Fix miscount of bandwidth event when reactivating previously unavailable RMID")?

Reinette

  parent reply	other threads:[~2025-12-05 21:57 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-04  2:37 [PATCH 0/2] x86/resctrl: Fix Platform QoS issues " Xiaochen Shen
2025-12-04  2:37 ` [PATCH 1/2] x86/resctrl: Add missing resctrl initialization " Xiaochen Shen
2025-12-06  3:30   ` Fenghua Yu
2025-12-06 10:47     ` Xiaochen Shen
2025-12-04  2:37 ` [PATCH 2/2] x86/resctrl: Fix memory bandwidth counter width " Xiaochen Shen
2025-12-04 17:11   ` Luck, Tony
2025-12-05  2:38     ` Xiaochen Shen
2025-12-05 20:33       ` Luck, Tony
2025-12-06 16:14         ` Xiaochen Shen
2025-12-07  2:26           ` Xiaochen Shen
2025-12-08 16:52           ` Luck, Tony
2025-12-07  0:56         ` Xiaochen Shen
2025-12-05 21:57       ` Reinette Chatre [this message]
2025-12-06 16:19         ` Xiaochen Shen
2025-12-04 23:30 ` [PATCH 0/2] x86/resctrl: Fix Platform QoS issues " Reinette Chatre
2025-12-05  2:47   ` Xiaochen Shen

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