From: Vignesh Raghavendra <vigneshr@ti.com>
To: Siddharth Vadapalli <s-vadapalli@ti.com>,
Roger Quadros <rogerq@kernel.org>
Cc: <nm@ti.com>, <afd@ti.com>, <kristo@kernel.org>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <u-kumar1@ti.com>,
<danishanwar@ti.com>, <srk@ti.com>
Subject: Re: [PATCH v5 1/7] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi
Date: Tue, 11 Jun 2024 14:40:43 +0530 [thread overview]
Message-ID: <9e7d3f9b-c762-40cd-9d0d-2f071aa3c371@ti.com> (raw)
In-Reply-To: <975c90b1-6657-40c6-a336-7f1f58acf531@ti.com>
On 11/06/24 14:24, Siddharth Vadapalli wrote:
> On Mon, Jun 10, 2024 at 10:31:07PM +0300, Roger Quadros wrote:
>
> [...]
>
>>> Based on your suggestion, you seem to propose the following hierarchy:
>>> k3-am62p-{main,mcu,thermal,wakeup}.dtsi = AM62P specific data
>>> k3-am62p.dtsi = k3-am62p-j722s-common-main.dtsi +
>>> k3-am62p-j722s-common-mcu.dtsi +
>>> k3-am62p-j722s-common-wakeup.dtsi +
>>> k3-am62p-j722s-common-thermal.dtsi +
>>> k3-am62p-{main,mcu,thermal,wakeup}.dtsi +
>>> <delta-5>
>>> k3-am62p5.dtsi = k3-am62p.dtsi + <delta-2>
>>> k3-j722s-{main,mcu,thermal,wakeup}.dtsi = J722S specific data
>>> k3-j722s.dtsi = k3-am62p-j722s-common-main.dtsi +
>>> k3-am62p-j722s-common-mcu.dtsi +
>>> k3-am62p-j722s-common-wakeup.dtsi +
>>> k3-am62p-j722s-common-thermal.dtsi +
>>> k3-j722s-{main,mcu,thermal,wakeup}.dtsi +
>>> <delta-6>
>>
>> What is the equivalent of k3-am62p5.dtsi here?
>> That should contain k3-j722s.dtsi + CPU and OPP stuff.
>>
>> I suppose it should be named specific to the SoC variant part number?
>
> AM62P (https://www.ti.com/product/AM62P) has two variants:
> 1. 2 Arm Cortex-A53 => AM62P3
> 2. 4 Arm Cortex-A53 => AM62P5
> Both variants will share the common k3-am62p.dtsi
>
> J722S (https://www.ti.com/product/TDA4VEN-Q1) has only one variant:
> 4 Arm Cortex-A53 => J722S
> Which is currently identical to AM62P5 w.r.t. the number of A53s.
>
> So there isn't an equivalent of AM62P5/k3-am62p5.dtsi for J722S.
> k3-j722s.dtsi is a combination of k3-am62p.dtsi and k3-am62p5.dtsi.
>
Historically AM6xx devices have had CPUs in separte file as there are OPNs with different number of CPU cores Hence, how about
k3-am62p5.dtsi => k3-am62p.dtsi + k3-am62p-j722s-common-{main,mcu,wakeup}.dtsi + k3-am62p-main.dtsi (USB2 and other deltas specific to AM62P)
and since J722s has no variants with less than 4 cores (and along the lines of rest of J7xx devices):
k3-j722s.dtsi => k3-am62p-j722s-common-{main,mcu,wakeup}.dtsi + k3-j722s-main.dtsi (USB3, C7x and other deltas specific to J722s;
--
Regards
Vignesh
next prev parent reply other threads:[~2024-06-11 9:11 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-04 8:52 [PATCH v5 0/7] Add PCIe, SERDES and USB DT support for J722S Siddharth Vadapalli
2024-06-04 8:52 ` [PATCH v5 1/7] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi Siddharth Vadapalli
2024-06-06 7:51 ` Roger Quadros
2024-06-07 11:28 ` Siddharth Vadapalli
2024-06-10 19:31 ` Roger Quadros
2024-06-11 8:54 ` Siddharth Vadapalli
2024-06-11 9:10 ` Vignesh Raghavendra [this message]
2024-06-11 17:18 ` Roger Quadros
2024-06-12 9:11 ` Siddharth Vadapalli
2024-06-04 8:52 ` [PATCH v5 2/7] arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to am62p-main.dtsi Siddharth Vadapalli
2024-06-06 8:01 ` Roger Quadros
2024-06-04 8:52 ` [PATCH v5 3/7] arm64: dts: ti: k3-j722s: Add main domain peripherals specific to J722S Siddharth Vadapalli
2024-06-06 8:02 ` Roger Quadros
2024-06-04 8:52 ` [PATCH v5 4/7] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common.dtsi Siddharth Vadapalli
2024-06-06 4:05 ` Vignesh Raghavendra
2024-06-06 7:34 ` Roger Quadros
2024-06-10 6:53 ` Vignesh Raghavendra
2024-06-04 8:52 ` [PATCH v5 5/7] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S Siddharth Vadapalli
2024-06-06 7:35 ` Roger Quadros
2024-06-04 8:52 ` [PATCH v5 6/7] arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support Siddharth Vadapalli
2024-06-06 8:04 ` Roger Quadros
2024-06-04 8:52 ` [PATCH v5 7/7] arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM Siddharth Vadapalli
2024-06-06 8:05 ` Roger Quadros
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=9e7d3f9b-c762-40cd-9d0d-2f071aa3c371@ti.com \
--to=vigneshr@ti.com \
--cc=afd@ti.com \
--cc=conor+dt@kernel.org \
--cc=danishanwar@ti.com \
--cc=devicetree@vger.kernel.org \
--cc=kristo@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=nm@ti.com \
--cc=robh@kernel.org \
--cc=rogerq@kernel.org \
--cc=s-vadapalli@ti.com \
--cc=srk@ti.com \
--cc=u-kumar1@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®