From: "Radim Krčmář" <radim.krcmar@oss.qualcomm.com>
To: <guodong.xu@oss.qualcomm.com>
Cc: "Charlie Jenkins" <thecharlesjenkins@gmail.com>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
"Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Andy Chiu" <andybnac@gmail.com>, "Zong Li" <zong.li@sifive.com>,
"Guodong Xu" <guodong.xu@linux.dev>
Subject: Re: [PATCH 1/6] riscv: hwprobe: Report FP extensions only when available
Date: Mon, 09 Nov 2026 14:40:30 +0100 [thread overview]
Message-ID: <DMQQ13TNRXGA.3KQXWTOX8OMCI@oss.qualcomm.com> (raw)
In-Reply-To: <qqvfduegawuoerrzwnj7drxkev63gxj4ddqaw4eqtrhsalugrd@sodih7ytwhos>
2026-11-07T23:16:20-05:00, <guodong.xu@oss.qualcomm.com>:
> Hi Radim,
>
> On 2026-10-07 09:46, Radim Krčmář wrote:
>>2026-10-06T16:54:53-07:00, Charlie Jenkins <thecharlesjenkins@gmail.com>:
>>>
>>> The vector Kconfig is gated on FPU=y so the vector instructions can't
>>> ever be enabled when FPU=n.
>>
>>Right, I'll make the commit message clearer in v2.
>>(Zve32x and hence has_vector() can technically exist without CONFIG_FPU,
>> so future implementations might require use to remove the dependency.)
>>
>
> Do you mean dropping "depends on FPU" from RISCV_ISA_V? Today it reads
> arch/riscv/Kconfig:
>
> config RISCV_ISA_V
> bool "Vector extension support"
> depends on TOOLCHAIN_HAS_V
> depends on FPU
>
> Today that dependency also gates Zve32x, Zve64x, Zvbb, Zvbc and the Zvk*,
> none of these touches floating-point state, but they are all being gated
> by CONFIG_FPU, that seems not correct.
>
> I noticed that the _validate() callbacks in today's cpufeature.c for these
> non-F (non-D) related extensions are checked against V only, but that
> doesn't change the fact that CONFIG_RISCV_ISA_V depends on CONFIG_FPU
> (from a commit 3 years ago) in Kconfig.
V extension does require F (V is Zve64d and at least 128 bit vlen), but
Zve32x that we use for _validate() and has_vector() is a subset of V, so
we could have a config for RISCV_ISA_ZVE32X that RISCV_ISA_V depends on.
I think it would be cleaner to have the ifdefery use RISCV_ISA_ZVE32X,
instead of reinterpreting RISCV_ISA_V to mean the base vector extension.
At the moment, I don't know of a requirement to have Linux builds with
Vector yet without FPU, so we can postpone the code churn...
We do support those F-less vector machines even now, just with a minor
overhead of dead FPU code.
My patch is only for machines where not all harts have F.
Thanks.
next prev parent reply other threads:[~2026-11-09 13:40 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-06 7:52 [PATCH 0/6] riscv: hwprobe: do not report disabled extensions Radim Krčmář
2026-10-06 7:52 ` [PATCH 1/6] riscv: hwprobe: Report FP extensions only when available Radim Krčmář
2026-10-06 23:54 ` Charlie Jenkins
2026-10-07 7:46 ` Radim Krčmář
2026-10-07 8:05 ` Charlie Jenkins
2026-11-08 4:16 ` guodong.xu
2026-11-09 13:40 ` Radim Krčmář [this message]
2026-10-16 21:04 ` Andy Chiu
2026-10-06 7:52 ` [PATCH 2/6] riscv: hwprobe: Report Zicbom and Zicboz " Radim Krčmář
2026-10-16 4:28 ` Charlie Jenkins
2026-10-16 21:06 ` Andy Chiu
2026-11-08 10:45 ` Guodong Xu
2026-10-06 7:53 ` [PATCH 3/6] riscv: hwprobe: Report Zicfilp and Zicfiss " Radim Krčmář
2026-10-16 4:28 ` Charlie Jenkins
2026-10-16 21:09 ` Andy Chiu
2026-11-08 10:05 ` Guodong Xu
2026-10-06 7:53 ` [PATCH 4/6] riscv: hwprobe: Report Supm " Radim Krčmář
2026-10-16 4:28 ` Charlie Jenkins
2026-10-16 21:26 ` Andy Chiu
2026-10-16 21:45 ` Andy Chiu
2026-10-20 10:00 ` Radim Krčmář
2026-11-08 11:24 ` [PATCH 4/6] " Guodong Xu
2026-11-09 13:41 ` Radim Krčmář
2026-10-06 7:53 ` [PATCH 5/6] riscv: hwprobe: Report XTheadVector " Radim Krčmář
2026-10-06 23:54 ` Charlie Jenkins
2026-10-07 7:59 ` Radim Krčmář
2026-10-07 8:07 ` Charlie Jenkins
2026-11-08 14:00 ` Guodong Xu
2026-10-16 21:48 ` Andy Chiu
2026-10-06 7:53 ` [PATCH 6/6] riscv: hwprobe: Report SiFive vector extensions " Radim Krčmář
2026-10-16 21:55 ` Andy Chiu
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