[PATCH] riscv: dts: sophgo: reduce SG2042 MSI count to 16

[PATCH] riscv: dts: sophgo: reduce SG2042 MSI count to 16

[Icenowy Zheng]

The SG2042 MSI controller has one 32-bit doorbell register, and each bit
corresponds to an interrupt. At a glance, it seems that the MSI
controller can support 32 interrupts; however the PCI MSI capability
only supports 16-bit messages, which makes the high 16 interrupts
unusable in such way.

Reduce the MSI count to 16 to prevent producing MSI message values that
cannot fit 16-bit integers.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 9fddf3f0b3b99..9f1820a7b5a9f 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -234,7 +234,7 @@ msi: msi-controller@7030010304 {
 			reg-names = "clr", "doorbell";
 			msi-controller;
 			#msi-cells = <0>;
-			msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>;
+			msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>;
 		};
 
 		rpgate: clock-controller@7030010368 {
-- 
2.52.0

Re: [PATCH] riscv: dts: sophgo: reduce SG2042 MSI count to 16

[Chen Wang]

On 4/8/2026 12:01 AM, Icenowy Zheng wrote:
> The SG2042 MSI controller has one 32-bit doorbell register, and each bit
> corresponds to an interrupt. At a glance, it seems that the MSI
> controller can support 32 interrupts; however the PCI MSI capability
> only supports 16-bit messages, which makes the high 16 interrupts
> unusable in such way.
>
> Reduce the MSI count to 16 to prevent producing MSI message values that
> cannot fit 16-bit integers.
>
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> ---
>   arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index 9fddf3f0b3b99..9f1820a7b5a9f 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -234,7 +234,7 @@ msi: msi-controller@7030010304 {
>   			reg-names = "clr", "doorbell";
>   			msi-controller;
>   			#msi-cells = <0>;
> -			msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>;
> +			msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>;
>   		};
>   
>   		rpgate: clock-controller@7030010368 {

LGTM.

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>

Tested-by: Chen Wang <unicorn_wang@outlook.com> on Pioneerbox.

Thanks,

Chen


Hi, Han,

Will you please run some quick test on EVB boards, I have no such 
hardware in hand, thanks.

Re: [PATCH] riscv: dts: sophgo: reduce SG2042 MSI count to 16

[Icenowy Zheng]

在 2026-04-08三的 15:04 +0800，Chen Wang写道：
> 
> On 4/8/2026 12:01 AM, Icenowy Zheng wrote:
> > The SG2042 MSI controller has one 32-bit doorbell register, and
> > each bit
> > corresponds to an interrupt. At a glance, it seems that the MSI
> > controller can support 32 interrupts; however the PCI MSI
> > capability
> > only supports 16-bit messages, which makes the high 16 interrupts
> > unusable in such way.
> > 
> > Reduce the MSI count to 16 to prevent producing MSI message values
> > that
> > cannot fit 16-bit integers.
> > 
> > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> > ---
> >   arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > index 9fddf3f0b3b99..9f1820a7b5a9f 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > @@ -234,7 +234,7 @@ msi: msi-controller@7030010304 {
> >   			reg-names = "clr", "doorbell";
> >   			msi-controller;
> >   			#msi-cells = <0>;
> > -			msi-ranges = <&intc 64
> > IRQ_TYPE_EDGE_RISING 32>;
> > +			msi-ranges = <&intc 64
> > IRQ_TYPE_EDGE_RISING 16>;
> >   		};
> >   
> >   		rpgate: clock-controller@7030010368 {
> 
> LGTM.
> 
> Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
> 
> Tested-by: Chen Wang <unicorn_wang@outlook.com> on Pioneerbox.
> 
> Thanks,
> 
> Chen
> 
> 
> Hi, Han,
> 
> Will you please run some quick test on EVB boards, I have no such 
> hardware in hand, thanks.

I tested on EVB v1, but I have no access to EVB v2 either.

Thanks,
Icenowy

> 
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH] riscv: dts: sophgo: reduce SG2042 MSI count to 16

[Inochi Amaoto]

On Wed, 08 Apr 2026 00:01:43 +0800, Icenowy Zheng wrote:
> The SG2042 MSI controller has one 32-bit doorbell register, and each bit
> corresponds to an interrupt. At a glance, it seems that the MSI
> controller can support 32 interrupts; however the PCI MSI capability
> only supports 16-bit messages, which makes the high 16 interrupts
> unusable in such way.
> 
> Reduce the MSI count to 16 to prevent producing MSI message values that
> cannot fit 16-bit integers.
> 
> [...]

Applied to for-next, thanks!

[1/1] riscv: dts: sophgo: reduce SG2042 MSI count to 16
      https://github.com/sophgo/linux/commit/903a9364e40563faf4730dc63ad7446246f494ff

Thanks,
Inochi