From: "Nutty.Liu" <nutty.liu@hotmail.com>
To: fangyu.yu@linux.alibaba.com, tomasz.jeznach@linux.dev,
joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de,
zong.li@sifive.com, andrew.jones@linux.dev, anup@brainfault.org,
jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com,
atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com,
joerg.roedel@amd.com, tanchi25@mails.ucas.ac.cn,
gong.shuai@sanechips.com.cn
Cc: guoren@kernel.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
kvm-riscv@lists.infradead.org
Subject: Re: [RFC PATCH v5 10/10] iommu/riscv: Add IOTINVAL.GVMA invalidations
Date: Tue, 27 Oct 2026 19:46:39 +0800 [thread overview]
Message-ID: <TYZPR04MB749148EDFFEE323B5280786FF3602@TYZPR04MB7491.apcprd04.prod.outlook.com> (raw)
In-Reply-To: <20261020094106.92722-11-fangyu.yu@linux.alibaba.com>
On 10/20/2026 5:41 PM, fangyu.yu@linux.alibaba.com wrote:
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
>
> Previously, only IOTINVAL.VMA was issued, which is insufficient for
> second-stage address translation consistency.
>
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Thanks,
Nutty
> ---
> drivers/iommu/riscv/iommu.c | 18 +++++++++++++++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
> index e3791e912af3..a764a172c588 100644
> --- a/drivers/iommu/riscv/iommu.c
> +++ b/drivers/iommu/riscv/iommu.c
> @@ -830,6 +830,15 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iommu_device *iommu,
> riscv_iommu_cmd_inval_vma(&cmd);
> riscv_iommu_cmd_send(iommu, &cmd);
>
> + /*
> + * Per the RISC-V IOMMU spec (sec. 5.5), the IOMMU may retain
> + * cached translations across mode switches. IOTINVAL.VMA only
> + * covers first-stage leaf PTEs, so use a global IOTINVAL.GVMA
> + * to flush stale second-stage translations.
> + */
> + riscv_iommu_cmd_inval_gvma(&cmd);
> + riscv_iommu_cmd_send(iommu, &cmd);
> +
> /* IOFENCE.C */
> riscv_iommu_cmd_sync(iommu, RISCV_IOMMU_IOTINVAL_TIMEOUT);
>
> @@ -1175,12 +1184,15 @@ static void riscv_iommu_iodir_iotinval(struct riscv_iommu_device *iommu,
> /*
> * else: IOTINVAL.VMA with GV=1,AV=PSCV=0,and
> * GSCID=DC.iohgatp.GSCID
> - *
> + */
> + riscv_iommu_cmd_send(iommu, &cmd);
> + /*
> * IOTINVAL.GVMA with GV=1,AV=0,and
> * GSCID=DC.iohgatp.GSCID
> - * TODO: For now, the Second-Stage feature have not yet been merged,
> - * also issue IOTINVAL.GVMA once second-stage support is merged.
> */
> + riscv_iommu_cmd_inval_gvma(&cmd);
> + riscv_iommu_cmd_inval_set_gscid(&cmd,
> + FIELD_GET(RISCV_IOMMU_DC_IOHGATP_GSCID, iohgatp));
> }
> riscv_iommu_cmd_send(iommu, &cmd);
> }
prev parent reply other threads:[~2026-10-27 11:46 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-20 9:40 [RFC PATCH v5 00/10] iommu/riscv: Add hardware dirty tracking for second-stage domains fangyu.yu
2026-10-20 9:40 ` [RFC PATCH v5 01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support fangyu.yu
2026-10-20 9:40 ` [RFC PATCH v5 02/10] iommupt: Add RISC-V dirty tracking PTE ops fangyu.yu
2026-10-20 9:40 ` [RFC PATCH v5 03/10] iommu/riscv: report iommu capabilities fangyu.yu
2026-10-20 9:41 ` [RFC PATCH v5 04/10] iommu/riscv: use data structure instead of individual values fangyu.yu
2026-10-20 9:41 ` [RFC PATCH v5 05/10] iommu/riscv: support GSCID and GVMA invalidation command fangyu.yu
2026-10-20 9:41 ` [RFC PATCH v5 06/10] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch fangyu.yu
2026-10-20 9:41 ` [RFC PATCH v5 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain fangyu.yu
2026-10-20 9:41 ` [RFC PATCH v5 08/10] iommu/riscv: Pre-enable GADE for second-stage domains fangyu.yu
2026-10-27 11:43 ` Nutty.Liu
2026-10-20 9:41 ` [RFC PATCH v5 09/10] iommu/riscv: Add dirty tracking support " fangyu.yu
2026-10-27 11:52 ` Nutty.Liu
2026-10-20 9:41 ` [RFC PATCH v5 10/10] iommu/riscv: Add IOTINVAL.GVMA invalidations fangyu.yu
2026-10-27 11:46 ` Nutty.Liu [this message]
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