[PATCH 0/2] clk: sunxi-ng: h616: Fix the EMAC 25 MHz and S/PDIF clocks

[PATCH 0/2] clk: sunxi-ng: h616: Fix the EMAC 25 MHz and S/PDIF clocks

[Arun Iyengar via B4 Relay]

Two small fixes for the H616 CCU, found while checking the clock tree of
an Orange Pi Zero2 against the H616 user manual.

Patch 1 models the EPHY 25 MHz clock as PLL_PERI0 / 24, as the manual
describes it. Only the parent and the reported rate change; the register
writes are the same.

Patch 2 lets the S/PDIF clock change the audio PLL rate, so the 44.1 kHz
and 48 kHz families both get the right module clock. It is the H616
counterpart of the H6 patch that was just applied [1].

Tested on an Orange Pi Zero2 (H616) with a 7.3 kernel carrying both
patches:
- clk_summary shows emac-25m at 25000000 with pll-periph0 (600 MHz) as
  its parent (200000000 below ahb3 before). The Zero2 uses an external
  RGMII PHY on EMAC0, so nothing on this board consumes the clock; only
  the clock tree was checked.
- With the S/PDIF output enabled, the spdif clock is 24576000 Hz under
  aplay at 48 kHz and 22579200 Hz at 44.1 kHz. I have no S/PDIF receiver,
  so the output itself was not checked on the wire.

These patches were developed with Claude (Anthropic) as a coding
assistant. It investigated the problem and wrote the code and the commit
messages; I reviewed them, and they were tested on an Orange Pi Zero2
(H616) as described above.

[1] https://lore.kernel.org/all/20261104185027.883011-1-jernej.skrabec@gmail.com/

---
Arun Iyengar (2):
      clk: sunxi-ng: h616: Fix the EMAC 25 MHz clock parent and divider
      clk: sunxi-ng: h616: Let the S/PDIF clock set the audio PLL rate

 drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)
---
base-commit: 280af24c860569000b375edda6436ba8e3ee4b3a
change-id: 20261110-h616-clk-emac-spdif-411c96dfbde2

Best regards,
--  
Arun Iyengar <aiyengar1990@gmail.com>

[PATCH 1/2] clk: sunxi-ng: h616: Fix the EMAC 25 MHz clock parent and divider

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

The H616 user manual (v1.0, 3.3.5.86 EPHY_25M_CLK_REG, 0x0970) gives the
EPHY 25 MHz clock as PLL_PERI0(1X) / 24, with bit 31 gating the output
and bit 30 gating the PLL_PERI0 input. The driver models it as a plain
gate below ahb3, so the clock framework reports the AHB3 rate (200 MHz)
for a clock that runs at 25 MHz, and the clock tree does not show that
the PHY clock depends on pll-periph0 rather than on the AHB3 bus.

Model it like the D1 driver does: a gate with a fixed /24 pre-divider
below pll-periph0. The register writes do not change, only the parent
and the reported rate do. On an Orange Pi Zero2, emac-25m now reads
25000000 with pll-periph0 (600 MHz) as its parent.

Fixes: 88dde5e23da1 ("clk: sunxi-ng: Add support for the Allwinner H616 CCU")
Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
index 955c614830fa..d2625fec651a 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
@@ -489,8 +489,17 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
 
-static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
-		      BIT(31) | BIT(30), 0);
+/*
+ * The EPHY 25 MHz clock is PLL_PERI0(1X) / 24, gated by both the special
+ * clock gate (bit 31) and the PLL_PERI0 input gate (bit 30).
+ */
+static const struct clk_hw *emac_25m_parents[] = {
+	&pll_periph0_clk.common.hw
+};
+
+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25m_clk, "emac-25m",
+				      emac_25m_parents, 0x970,
+				      BIT(31) | BIT(30), 24, 0);
 
 static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0), 0);
 static SUNXI_CCU_GATE(bus_emac1_clk, "bus-emac1", "ahb3", 0x97c, BIT(1), 0);

-- 
2.55.0

[PATCH 2/2] clk: sunxi-ng: h616: Let the S/PDIF clock set the audio PLL rate

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

sun4i-spdif asks for 22.5792 or 24.576 MHz on the S/PDIF (OWA) module
clock, depending on the sample rate family. The spdif clock has no
CLK_SET_RATE_PARENT, so it can only divide down the rate pll-audio
already runs at. Unless another audio device has already set the PLL for
the right family, the power-of-two divider rounds down and the request
succeeds at a wrong rate: about 12.3 MHz from the reset PLL value, so
48 kHz content is sent at about 24 kHz.

Propagate rate changes to the parent, like the audio codec clocks
already do. This is the same change as the one just applied for the H6
[1].

Link: https://lore.kernel.org/all/20261104185027.883011-1-jernej.skrabec@gmail.com/ [1]
Fixes: 88dde5e23da1 ("clk: sunxi-ng: Add support for the Allwinner H616 CCU")
Cc: stable@vger.kernel.org
Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
index d2625fec651a..f703d690a563 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
@@ -529,7 +529,7 @@ static struct ccu_div spdif_clk = {
 		.hw.init	= CLK_HW_INIT_PARENTS("spdif",
 						      audio_parents,
 						      &ccu_div_ops,
-						      0),
+						      CLK_SET_RATE_PARENT),
 	},
 };
 

-- 
2.55.0

Re: [PATCH 2/2] clk: sunxi-ng: h616: Let the S/PDIF clock set the audio PLL rate

[Jernej Škrabec]

Dne torek, 10. november 2026 ob 07:03:01 Srednjeevropski standardni čas je Arun Iyengar via B4 Relay napisal(a):
> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> sun4i-spdif asks for 22.5792 or 24.576 MHz on the S/PDIF (OWA) module
> clock, depending on the sample rate family. The spdif clock has no
> CLK_SET_RATE_PARENT, so it can only divide down the rate pll-audio
> already runs at. Unless another audio device has already set the PLL for
> the right family, the power-of-two divider rounds down and the request
> succeeds at a wrong rate: about 12.3 MHz from the reset PLL value, so
> 48 kHz content is sent at about 24 kHz.
> 
> Propagate rate changes to the parent, like the audio codec clocks
> already do. This is the same change as the one just applied for the H6
> [1].
> 
> Link: https://lore.kernel.org/all/20261104185027.883011-1-jernej.skrabec@gmail.com/ [1]

There is no need to link to H6 patch. It's clear that patch is needed.

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

> Fixes: 88dde5e23da1 ("clk: sunxi-ng: Add support for the Allwinner H616 CCU")
> Cc: stable@vger.kernel.org
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---
>  drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> index d2625fec651a..f703d690a563 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> @@ -529,7 +529,7 @@ static struct ccu_div spdif_clk = {
>  		.hw.init	= CLK_HW_INIT_PARENTS("spdif",
>  						      audio_parents,
>  						      &ccu_div_ops,
> -						      0),
> +						      CLK_SET_RATE_PARENT),
>  	},
>  };
>  
> 
> 

Re: [PATCH 1/2] clk: sunxi-ng: h616: Fix the EMAC 25 MHz clock parent and divider

[Jernej Škrabec]

Dne torek, 10. november 2026 ob 07:03:00 Srednjeevropski standardni čas je Arun Iyengar via B4 Relay napisal(a):
> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> The H616 user manual (v1.0, 3.3.5.86 EPHY_25M_CLK_REG, 0x0970) gives the
> EPHY 25 MHz clock as PLL_PERI0(1X) / 24, with bit 31 gating the output
> and bit 30 gating the PLL_PERI0 input. The driver models it as a plain
> gate below ahb3, so the clock framework reports the AHB3 rate (200 MHz)
> for a clock that runs at 25 MHz, and the clock tree does not show that
> the PHY clock depends on pll-periph0 rather than on the AHB3 bus.
> 
> Model it like the D1 driver does: a gate with a fixed /24 pre-divider
> below pll-periph0. The register writes do not change, only the parent
> and the reported rate do. On an Orange Pi Zero2, emac-25m now reads
> 25000000 with pll-periph0 (600 MHz) as its parent.
> 
> Fixes: 88dde5e23da1 ("clk: sunxi-ng: Add support for the Allwinner H616 CCU")
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

> ---
>  drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> index 955c614830fa..d2625fec651a 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> @@ -489,8 +489,17 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
>  static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
>  static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
>  
> -static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
> -		      BIT(31) | BIT(30), 0);
> +/*
> + * The EPHY 25 MHz clock is PLL_PERI0(1X) / 24, gated by both the special
> + * clock gate (bit 31) and the PLL_PERI0 input gate (bit 30).
> + */
> +static const struct clk_hw *emac_25m_parents[] = {
> +	&pll_periph0_clk.common.hw
> +};
> +
> +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25m_clk, "emac-25m",
> +				      emac_25m_parents, 0x970,
> +				      BIT(31) | BIT(30), 24, 0);
>  
>  static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0), 0);
>  static SUNXI_CCU_GATE(bus_emac1_clk, "bus-emac1", "ahb3", 0x97c, BIT(1), 0);
> 
>