* [PATCH v2 0/2] drm/tegra: Support YVU420
@ 2026-10-18 22:03 Aaron Kling via B4 Relay
2026-10-18 22:03 ` [PATCH v2 1/2] drm/tegra: Support swapping chroma planes Aaron Kling via B4 Relay
2026-10-18 22:03 ` [PATCH v2 2/2] drm/tegra: Support YVU420 Aaron Kling via B4 Relay
0 siblings, 2 replies; 6+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-10-18 22:03 UTC (permalink / raw)
To: Thierry Reding, Mikko Perttunen, David Airlie, Simona Vetter,
Jonathan Hunter
Cc: dri-devel, linux-tegra, linux-kernel, Aaron Kling
This is not directly supported by the display controller hardware.
However, this can be handled efficiently by just passing the chroma
planes to the hardware backwards and reporting it as yuv420.
The format is required by AOSP for software decoded video playback among
other things. An attempt was made to handle this in gralloc by swapping
the chroma planes there, but it wasn't working. This kernel
implementation is working and is more generic anyways. This has been
verified on a SHIELD TV 2019 Pro for the tegradc path and a Jetson TX2
NX for the nvdisplay path.
---
Changes in v2:
- In patch 1, simplify pre-nvdisplay path to a swap of the window base
address
- In patch 1, address sashiko report about failure to copy the new
struct entry in duplicate_state
- In patch 2, address sashiko report that yvu420 was missing from
tegra20_overlays when the targets already support yuv420.
- Link to v1: https://lore.kernel.org/r/20261008-tegra-drm-yvu420-v1-0-dc1c443c00f3@gmail.com
---
Aaron Kling (2):
drm/tegra: Support swapping chroma planes
drm/tegra: Support YVU420
drivers/gpu/drm/tegra/dc.c | 9 ++++++++-
drivers/gpu/drm/tegra/hub.c | 15 ++++++++++-----
drivers/gpu/drm/tegra/plane.c | 13 ++++++++++++-
drivers/gpu/drm/tegra/plane.h | 3 ++-
4 files changed, 32 insertions(+), 8 deletions(-)
---
base-commit: 2efb7a11f1aa4d2dc285fe2680cca22cb9f72f64
change-id: 20261008-tegra-drm-yvu420-1dbb7140e54a
Best regards,
--
Aaron Kling <webgeek1234@gmail.com>
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 1/2] drm/tegra: Support swapping chroma planes 2026-10-18 22:03 [PATCH v2 0/2] drm/tegra: Support YVU420 Aaron Kling via B4 Relay @ 2026-10-18 22:03 ` Aaron Kling via B4 Relay 2026-10-20 5:08 ` Mikko Perttunen 2026-10-18 22:03 ` [PATCH v2 2/2] drm/tegra: Support YVU420 Aaron Kling via B4 Relay 1 sibling, 1 reply; 6+ messages in thread From: Aaron Kling via B4 Relay @ 2026-10-18 22:03 UTC (permalink / raw) To: Thierry Reding, Mikko Perttunen, David Airlie, Simona Vetter, Jonathan Hunter Cc: dri-devel, linux-tegra, linux-kernel, Aaron Kling From: Aaron Kling <webgeek1234@gmail.com> The Tegra display controller supports some yuv types, but not their chroma swapped variants. For example, yuv420 is supported but yvu420 is not. This can be efficiently worked around by just passing the hardware said chroma planes backwards. Add a flag to the plane state struct and handling to both tegradc and nvdisplay paths. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> --- drivers/gpu/drm/tegra/dc.c | 6 +++++- drivers/gpu/drm/tegra/hub.c | 14 +++++++++----- drivers/gpu/drm/tegra/plane.c | 5 ++++- drivers/gpu/drm/tegra/plane.h | 3 ++- 4 files changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index b0bfa946e6979..39c2e920d76a6 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -740,7 +740,8 @@ static int tegra_plane_atomic_check(struct drm_plane *plane, err = tegra_plane_format(new_plane_state->fb->format->format, &plane_state->format, - &plane_state->swap); + &plane_state->swap, + &plane_state->swap_uv); if (err < 0) return err; @@ -872,6 +873,9 @@ static void tegra_plane_atomic_update(struct drm_plane *plane, window.stride[i] = fb->pitches[i]; } + if (tegra_plane_state->swap_uv) + swap(window.base[1], window.base[2]); + tegra_dc_setup_window(p, &window); } diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c index 448f49f3a7d7e..6427155ac4fdf 100644 --- a/drivers/gpu/drm/tegra/hub.c +++ b/drivers/gpu/drm/tegra/hub.c @@ -440,7 +440,8 @@ static int tegra_shared_plane_atomic_check(struct drm_plane *plane, err = tegra_plane_format(new_plane_state->fb->format->format, &plane_state->format, - &plane_state->swap); + &plane_state->swap, + &plane_state->swap_uv); if (err < 0) return err; @@ -664,24 +665,27 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane, tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE); if (yuv && planes > 1) { - base = tegra_plane_state->iova[1] + fb->offsets[1]; + uint8_t u = tegra_plane_state->swap_uv ? 2 : 1; + uint8_t v = tegra_plane_state->swap_uv ? 1 : 2; + + base = tegra_plane_state->iova[u] + fb->offsets[u]; base |= addr_flag; tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U); tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U); if (planes > 2) { - base = tegra_plane_state->iova[2] + fb->offsets[2]; + base = tegra_plane_state->iova[v] + fb->offsets[v]; base |= addr_flag; tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V); tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V); } - value = PITCH_U(fb->pitches[1]); + value = PITCH_U(fb->pitches[u]); if (planes > 2) - value |= PITCH_V(fb->pitches[2]); + value |= PITCH_V(fb->pitches[v]); tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV); } else { diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c index 2148b0c59815c..757bc552809fe 100644 --- a/drivers/gpu/drm/tegra/plane.c +++ b/drivers/gpu/drm/tegra/plane.c @@ -59,6 +59,7 @@ tegra_plane_atomic_duplicate_state(struct drm_plane *plane) copy->tiling = state->tiling; copy->format = state->format; copy->swap = state->swap; + copy->swap_uv = state->swap_uv; copy->reflect_x = state->reflect_x; copy->reflect_y = state->reflect_y; copy->opaque = state->opaque; @@ -319,11 +320,13 @@ int tegra_plane_state_add(struct tegra_plane *plane, return 0; } -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap) +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv) { /* assume no swapping of fetched data */ if (swap) *swap = BYTE_SWAP_NOSWAP; + if (swap_uv) + *swap_uv = false; switch (fourcc) { case DRM_FORMAT_ARGB4444: diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h index e33a581e6490e..dba5f1b254e98 100644 --- a/drivers/gpu/drm/tegra/plane.h +++ b/drivers/gpu/drm/tegra/plane.h @@ -49,6 +49,7 @@ struct tegra_plane_state { struct tegra_bo_tiling tiling; u32 format; u32 swap; + bool swap_uv; bool reflect_x; bool reflect_y; @@ -88,7 +89,7 @@ void tegra_plane_cleanup_fb(struct drm_plane *plane, int tegra_plane_state_add(struct tegra_plane *plane, struct drm_plane_state *state); -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap); +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv); bool tegra_plane_format_is_indexed(unsigned int format); bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes, unsigned int *bpc); int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, -- 2.54.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] drm/tegra: Support swapping chroma planes 2026-10-18 22:03 ` [PATCH v2 1/2] drm/tegra: Support swapping chroma planes Aaron Kling via B4 Relay @ 2026-10-20 5:08 ` Mikko Perttunen 2026-10-20 5:59 ` Aaron Kling 0 siblings, 1 reply; 6+ messages in thread From: Mikko Perttunen @ 2026-10-20 5:08 UTC (permalink / raw) To: Thierry Reding, David Airlie, Simona Vetter, Jonathan Hunter, webgeek1234 Cc: dri-devel, linux-tegra, linux-kernel, Aaron Kling On Monday, October 19, 2026 7:03 AM Aaron Kling via B4 Relay wrote: > From: Aaron Kling <webgeek1234@gmail.com> > > The Tegra display controller supports some yuv types, but not their > chroma swapped variants. For example, yuv420 is supported but yvu420 is > not. This can be efficiently worked around by just passing the hardware > said chroma planes backwards. Add a flag to the plane state struct and > handling to both tegradc and nvdisplay paths. > > Signed-off-by: Aaron Kling <webgeek1234@gmail.com> > --- > drivers/gpu/drm/tegra/dc.c | 6 +++++- > drivers/gpu/drm/tegra/hub.c | 14 +++++++++----- > drivers/gpu/drm/tegra/plane.c | 5 ++++- > drivers/gpu/drm/tegra/plane.h | 3 ++- > 4 files changed, 20 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c > index b0bfa946e6979..39c2e920d76a6 100644 > --- a/drivers/gpu/drm/tegra/dc.c > +++ b/drivers/gpu/drm/tegra/dc.c > @@ -740,7 +740,8 @@ static int tegra_plane_atomic_check(struct drm_plane *plane, > > err = tegra_plane_format(new_plane_state->fb->format->format, > &plane_state->format, > - &plane_state->swap); > + &plane_state->swap, > + &plane_state->swap_uv); > if (err < 0) > return err; > > @@ -872,6 +873,9 @@ static void tegra_plane_atomic_update(struct drm_plane *plane, > window.stride[i] = fb->pitches[i]; > } > > + if (tegra_plane_state->swap_uv) > + swap(window.base[1], window.base[2]); > + > tegra_dc_setup_window(p, &window); > } > > diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c > index 448f49f3a7d7e..6427155ac4fdf 100644 > --- a/drivers/gpu/drm/tegra/hub.c > +++ b/drivers/gpu/drm/tegra/hub.c > @@ -440,7 +440,8 @@ static int tegra_shared_plane_atomic_check(struct drm_plane *plane, > > err = tegra_plane_format(new_plane_state->fb->format->format, > &plane_state->format, > - &plane_state->swap); > + &plane_state->swap, > + &plane_state->swap_uv); > if (err < 0) > return err; > > @@ -664,24 +665,27 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane, > tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE); > > if (yuv && planes > 1) { > - base = tegra_plane_state->iova[1] + fb->offsets[1]; > + uint8_t u = tegra_plane_state->swap_uv ? 2 : 1; > + uint8_t v = tegra_plane_state->swap_uv ? 1 : 2; > + > + base = tegra_plane_state->iova[u] + fb->offsets[u]; > base |= addr_flag; > > tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U); > tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U); > > if (planes > 2) { > - base = tegra_plane_state->iova[2] + fb->offsets[2]; > + base = tegra_plane_state->iova[v] + fb->offsets[v]; > base |= addr_flag; > > tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V); > tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V); > } > > - value = PITCH_U(fb->pitches[1]); > + value = PITCH_U(fb->pitches[u]); > > if (planes > 2) > - value |= PITCH_V(fb->pitches[2]); > + value |= PITCH_V(fb->pitches[v]); > > tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV); > } else { I noticed DC_WIN_PRECOMP_WGRP_PARAMS has a SWAP_UV bit. This is already defined in dc.h. So we can use that for the hub.c implementation instead of manually swapping. Otherwise everything looks good to me. We could also enable the swap_uv logic for other UV formats. Cheers Mikko > diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c > index 2148b0c59815c..757bc552809fe 100644 > --- a/drivers/gpu/drm/tegra/plane.c > +++ b/drivers/gpu/drm/tegra/plane.c > @@ -59,6 +59,7 @@ tegra_plane_atomic_duplicate_state(struct drm_plane *plane) > copy->tiling = state->tiling; > copy->format = state->format; > copy->swap = state->swap; > + copy->swap_uv = state->swap_uv; > copy->reflect_x = state->reflect_x; > copy->reflect_y = state->reflect_y; > copy->opaque = state->opaque; > @@ -319,11 +320,13 @@ int tegra_plane_state_add(struct tegra_plane *plane, > return 0; > } > > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap) > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv) > { > /* assume no swapping of fetched data */ > if (swap) > *swap = BYTE_SWAP_NOSWAP; > + if (swap_uv) > + *swap_uv = false; > > switch (fourcc) { > case DRM_FORMAT_ARGB4444: > diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h > index e33a581e6490e..dba5f1b254e98 100644 > --- a/drivers/gpu/drm/tegra/plane.h > +++ b/drivers/gpu/drm/tegra/plane.h > @@ -49,6 +49,7 @@ struct tegra_plane_state { > struct tegra_bo_tiling tiling; > u32 format; > u32 swap; > + bool swap_uv; > > bool reflect_x; > bool reflect_y; > @@ -88,7 +89,7 @@ void tegra_plane_cleanup_fb(struct drm_plane *plane, > int tegra_plane_state_add(struct tegra_plane *plane, > struct drm_plane_state *state); > > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap); > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv); > bool tegra_plane_format_is_indexed(unsigned int format); > bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes, unsigned int *bpc); > int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, > > -- > 2.54.0 > > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] drm/tegra: Support swapping chroma planes 2026-10-20 5:08 ` Mikko Perttunen @ 2026-10-20 5:59 ` Aaron Kling 2026-10-20 6:33 ` Mikko Perttunen 0 siblings, 1 reply; 6+ messages in thread From: Aaron Kling @ 2026-10-20 5:59 UTC (permalink / raw) To: Mikko Perttunen Cc: Thierry Reding, David Airlie, Simona Vetter, Jonathan Hunter, dri-devel, linux-tegra, linux-kernel On Tue, Oct 20, 2026 at 12:08 AM Mikko Perttunen <mperttunen@nvidia.com> wrote: > > On Monday, October 19, 2026 7:03 AM Aaron Kling via B4 Relay wrote: > > From: Aaron Kling <webgeek1234@gmail.com> > > > > The Tegra display controller supports some yuv types, but not their > > chroma swapped variants. For example, yuv420 is supported but yvu420 is > > not. This can be efficiently worked around by just passing the hardware > > said chroma planes backwards. Add a flag to the plane state struct and > > handling to both tegradc and nvdisplay paths. > > > > Signed-off-by: Aaron Kling <webgeek1234@gmail.com> > > --- > > drivers/gpu/drm/tegra/dc.c | 6 +++++- > > drivers/gpu/drm/tegra/hub.c | 14 +++++++++----- > > drivers/gpu/drm/tegra/plane.c | 5 ++++- > > drivers/gpu/drm/tegra/plane.h | 3 ++- > > 4 files changed, 20 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c > > index b0bfa946e6979..39c2e920d76a6 100644 > > --- a/drivers/gpu/drm/tegra/dc.c > > +++ b/drivers/gpu/drm/tegra/dc.c > > @@ -740,7 +740,8 @@ static int tegra_plane_atomic_check(struct drm_plane *plane, > > > > err = tegra_plane_format(new_plane_state->fb->format->format, > > &plane_state->format, > > - &plane_state->swap); > > + &plane_state->swap, > > + &plane_state->swap_uv); > > if (err < 0) > > return err; > > > > @@ -872,6 +873,9 @@ static void tegra_plane_atomic_update(struct drm_plane *plane, > > window.stride[i] = fb->pitches[i]; > > } > > > > + if (tegra_plane_state->swap_uv) > > + swap(window.base[1], window.base[2]); > > + > > tegra_dc_setup_window(p, &window); > > } > > > > diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c > > index 448f49f3a7d7e..6427155ac4fdf 100644 > > --- a/drivers/gpu/drm/tegra/hub.c > > +++ b/drivers/gpu/drm/tegra/hub.c > > @@ -440,7 +440,8 @@ static int tegra_shared_plane_atomic_check(struct drm_plane *plane, > > > > err = tegra_plane_format(new_plane_state->fb->format->format, > > &plane_state->format, > > - &plane_state->swap); > > + &plane_state->swap, > > + &plane_state->swap_uv); > > if (err < 0) > > return err; > > > > @@ -664,24 +665,27 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane, > > tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE); > > > > if (yuv && planes > 1) { > > - base = tegra_plane_state->iova[1] + fb->offsets[1]; > > + uint8_t u = tegra_plane_state->swap_uv ? 2 : 1; > > + uint8_t v = tegra_plane_state->swap_uv ? 1 : 2; > > + > > + base = tegra_plane_state->iova[u] + fb->offsets[u]; > > base |= addr_flag; > > > > tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U); > > tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U); > > > > if (planes > 2) { > > - base = tegra_plane_state->iova[2] + fb->offsets[2]; > > + base = tegra_plane_state->iova[v] + fb->offsets[v]; > > base |= addr_flag; > > > > tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V); > > tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V); > > } > > > > - value = PITCH_U(fb->pitches[1]); > > + value = PITCH_U(fb->pitches[u]); > > > > if (planes > 2) > > - value |= PITCH_V(fb->pitches[2]); > > + value |= PITCH_V(fb->pitches[v]); > > > > tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV); > > } else { > > I noticed DC_WIN_PRECOMP_WGRP_PARAMS has a SWAP_UV bit. This is already > defined in dc.h. So we can use that for the hub.c implementation instead > of manually swapping. Oh. I figured there had to be something like that in one of the generations, but my grep-fu failed me. Even more embarrassing that I ended up using the exact same name. I will update and verify this and send a new revision. > Otherwise everything looks good to me. We could also enable the swap_uv > logic for other UV formats. Eh, other than asking for the entire patch to be rewritten over the last two revisions, it looks good. :P And alright, I'll plumb yvu422 and yvu444 in the new revision as well. However, I don't have test cases for those. Aaron > Cheers > Mikko > > > diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c > > index 2148b0c59815c..757bc552809fe 100644 > > --- a/drivers/gpu/drm/tegra/plane.c > > +++ b/drivers/gpu/drm/tegra/plane.c > > @@ -59,6 +59,7 @@ tegra_plane_atomic_duplicate_state(struct drm_plane *plane) > > copy->tiling = state->tiling; > > copy->format = state->format; > > copy->swap = state->swap; > > + copy->swap_uv = state->swap_uv; > > copy->reflect_x = state->reflect_x; > > copy->reflect_y = state->reflect_y; > > copy->opaque = state->opaque; > > @@ -319,11 +320,13 @@ int tegra_plane_state_add(struct tegra_plane *plane, > > return 0; > > } > > > > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap) > > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv) > > { > > /* assume no swapping of fetched data */ > > if (swap) > > *swap = BYTE_SWAP_NOSWAP; > > + if (swap_uv) > > + *swap_uv = false; > > > > switch (fourcc) { > > case DRM_FORMAT_ARGB4444: > > diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h > > index e33a581e6490e..dba5f1b254e98 100644 > > --- a/drivers/gpu/drm/tegra/plane.h > > +++ b/drivers/gpu/drm/tegra/plane.h > > @@ -49,6 +49,7 @@ struct tegra_plane_state { > > struct tegra_bo_tiling tiling; > > u32 format; > > u32 swap; > > + bool swap_uv; > > > > bool reflect_x; > > bool reflect_y; > > @@ -88,7 +89,7 @@ void tegra_plane_cleanup_fb(struct drm_plane *plane, > > int tegra_plane_state_add(struct tegra_plane *plane, > > struct drm_plane_state *state); > > > > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap); > > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv); > > bool tegra_plane_format_is_indexed(unsigned int format); > > bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes, unsigned int *bpc); > > int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, > > > > -- > > 2.54.0 > > > > > > > > > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] drm/tegra: Support swapping chroma planes 2026-10-20 5:59 ` Aaron Kling @ 2026-10-20 6:33 ` Mikko Perttunen 0 siblings, 0 replies; 6+ messages in thread From: Mikko Perttunen @ 2026-10-20 6:33 UTC (permalink / raw) To: linux-tegra Cc: Thierry Reding, David Airlie, Simona Vetter, Jonathan Hunter, dri-devel, linux-tegra, linux-kernel, Aaron Kling On Tuesday, October 20, 2026 2:59 PM Aaron Kling wrote: > On Tue, Oct 20, 2026 at 12:08 AM Mikko Perttunen <mperttunen@nvidia.com> wrote: > > > > On Monday, October 19, 2026 7:03 AM Aaron Kling via B4 Relay wrote: > > > From: Aaron Kling <webgeek1234@gmail.com> > > > > > > The Tegra display controller supports some yuv types, but not their > > > chroma swapped variants. For example, yuv420 is supported but yvu420 is > > > not. This can be efficiently worked around by just passing the hardware > > > said chroma planes backwards. Add a flag to the plane state struct and > > > handling to both tegradc and nvdisplay paths. > > > > > > Signed-off-by: Aaron Kling <webgeek1234@gmail.com> > > > --- > > > drivers/gpu/drm/tegra/dc.c | 6 +++++- > > > drivers/gpu/drm/tegra/hub.c | 14 +++++++++----- > > > drivers/gpu/drm/tegra/plane.c | 5 ++++- > > > drivers/gpu/drm/tegra/plane.h | 3 ++- > > > 4 files changed, 20 insertions(+), 8 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c > > > index b0bfa946e6979..39c2e920d76a6 100644 > > > --- a/drivers/gpu/drm/tegra/dc.c > > > +++ b/drivers/gpu/drm/tegra/dc.c > > > @@ -740,7 +740,8 @@ static int tegra_plane_atomic_check(struct drm_plane *plane, > > > > > > err = tegra_plane_format(new_plane_state->fb->format->format, > > > &plane_state->format, > > > - &plane_state->swap); > > > + &plane_state->swap, > > > + &plane_state->swap_uv); > > > if (err < 0) > > > return err; > > > > > > @@ -872,6 +873,9 @@ static void tegra_plane_atomic_update(struct drm_plane *plane, > > > window.stride[i] = fb->pitches[i]; > > > } > > > > > > + if (tegra_plane_state->swap_uv) > > > + swap(window.base[1], window.base[2]); > > > + > > > tegra_dc_setup_window(p, &window); > > > } > > > > > > diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c > > > index 448f49f3a7d7e..6427155ac4fdf 100644 > > > --- a/drivers/gpu/drm/tegra/hub.c > > > +++ b/drivers/gpu/drm/tegra/hub.c > > > @@ -440,7 +440,8 @@ static int tegra_shared_plane_atomic_check(struct drm_plane *plane, > > > > > > err = tegra_plane_format(new_plane_state->fb->format->format, > > > &plane_state->format, > > > - &plane_state->swap); > > > + &plane_state->swap, > > > + &plane_state->swap_uv); > > > if (err < 0) > > > return err; > > > > > > @@ -664,24 +665,27 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane, > > > tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE); > > > > > > if (yuv && planes > 1) { > > > - base = tegra_plane_state->iova[1] + fb->offsets[1]; > > > + uint8_t u = tegra_plane_state->swap_uv ? 2 : 1; > > > + uint8_t v = tegra_plane_state->swap_uv ? 1 : 2; > > > + > > > + base = tegra_plane_state->iova[u] + fb->offsets[u]; > > > base |= addr_flag; > > > > > > tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U); > > > tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U); > > > > > > if (planes > 2) { > > > - base = tegra_plane_state->iova[2] + fb->offsets[2]; > > > + base = tegra_plane_state->iova[v] + fb->offsets[v]; > > > base |= addr_flag; > > > > > > tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V); > > > tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V); > > > } > > > > > > - value = PITCH_U(fb->pitches[1]); > > > + value = PITCH_U(fb->pitches[u]); > > > > > > if (planes > 2) > > > - value |= PITCH_V(fb->pitches[2]); > > > + value |= PITCH_V(fb->pitches[v]); > > > > > > tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV); > > > } else { > > > > I noticed DC_WIN_PRECOMP_WGRP_PARAMS has a SWAP_UV bit. This is already > > defined in dc.h. So we can use that for the hub.c implementation instead > > of manually swapping. > > Oh. I figured there had to be something like that in one of the > generations, but my grep-fu failed me. Even more embarrassing that I > ended up using the exact same name. I will update and verify this and > send a new revision. > > > Otherwise everything looks good to me. We could also enable the swap_uv > > logic for other UV formats. > > Eh, other than asking for the entire patch to be rewritten over the > last two revisions, it looks good. :P And alright, I'll plumb yvu422 > and yvu444 in the new revision as well. However, I don't have test > cases for those. These are minor revisions, pretty much cosmetic! :) If you have access to the libdrm modetest command, you can use it to test -- e.g. sudo modetest -M tegra -s 78:1920x1080 \ -P 44@43:896x504+40+288@YU12 \ -P 48@43:896x504+984+288@YV12 (the ID numbers may differ) to set up a 1920x1080 mode with two overlay planes one with each plane ordering. BTW, I believe the hardware swap bit also supports packed and semiplanar formats -- you can add those too if you'd like or leave them out and we can add them later if needed. Mikko > > Aaron > > > Cheers > > Mikko > > > > > diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c > > > index 2148b0c59815c..757bc552809fe 100644 > > > --- a/drivers/gpu/drm/tegra/plane.c > > > +++ b/drivers/gpu/drm/tegra/plane.c > > > @@ -59,6 +59,7 @@ tegra_plane_atomic_duplicate_state(struct drm_plane *plane) > > > copy->tiling = state->tiling; > > > copy->format = state->format; > > > copy->swap = state->swap; > > > + copy->swap_uv = state->swap_uv; > > > copy->reflect_x = state->reflect_x; > > > copy->reflect_y = state->reflect_y; > > > copy->opaque = state->opaque; > > > @@ -319,11 +320,13 @@ int tegra_plane_state_add(struct tegra_plane *plane, > > > return 0; > > > } > > > > > > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap) > > > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv) > > > { > > > /* assume no swapping of fetched data */ > > > if (swap) > > > *swap = BYTE_SWAP_NOSWAP; > > > + if (swap_uv) > > > + *swap_uv = false; > > > > > > switch (fourcc) { > > > case DRM_FORMAT_ARGB4444: > > > diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h > > > index e33a581e6490e..dba5f1b254e98 100644 > > > --- a/drivers/gpu/drm/tegra/plane.h > > > +++ b/drivers/gpu/drm/tegra/plane.h > > > @@ -49,6 +49,7 @@ struct tegra_plane_state { > > > struct tegra_bo_tiling tiling; > > > u32 format; > > > u32 swap; > > > + bool swap_uv; > > > > > > bool reflect_x; > > > bool reflect_y; > > > @@ -88,7 +89,7 @@ void tegra_plane_cleanup_fb(struct drm_plane *plane, > > > int tegra_plane_state_add(struct tegra_plane *plane, > > > struct drm_plane_state *state); > > > > > > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap); > > > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv); > > > bool tegra_plane_format_is_indexed(unsigned int format); > > > bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes, unsigned int *bpc); > > > int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, > > > > > > -- > > > 2.54.0 > > > > > > > > > > > > > > > > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] drm/tegra: Support YVU420 2026-10-18 22:03 [PATCH v2 0/2] drm/tegra: Support YVU420 Aaron Kling via B4 Relay 2026-10-18 22:03 ` [PATCH v2 1/2] drm/tegra: Support swapping chroma planes Aaron Kling via B4 Relay @ 2026-10-18 22:03 ` Aaron Kling via B4 Relay 1 sibling, 0 replies; 6+ messages in thread From: Aaron Kling via B4 Relay @ 2026-10-18 22:03 UTC (permalink / raw) To: Thierry Reding, Mikko Perttunen, David Airlie, Simona Vetter, Jonathan Hunter Cc: dri-devel, linux-tegra, linux-kernel, Aaron Kling From: Aaron Kling <webgeek1234@gmail.com> This format is used by AOSP for video playback among other things. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> --- drivers/gpu/drm/tegra/dc.c | 3 +++ drivers/gpu/drm/tegra/hub.c | 1 + drivers/gpu/drm/tegra/plane.c | 8 ++++++++ 3 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 39c2e920d76a6..61e155ecbfcb7 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1282,6 +1282,7 @@ static const u32 tegra20_overlay_formats[] = { DRM_FORMAT_YUYV, DRM_FORMAT_YUV420, DRM_FORMAT_YUV422, + DRM_FORMAT_YVU420, }; static const u32 tegra114_overlay_formats[] = { @@ -1309,6 +1310,7 @@ static const u32 tegra114_overlay_formats[] = { DRM_FORMAT_YUYV, DRM_FORMAT_YUV420, DRM_FORMAT_YUV422, + DRM_FORMAT_YVU420, /* semi-planar formats */ DRM_FORMAT_NV12, DRM_FORMAT_NV21, @@ -1349,6 +1351,7 @@ static const u32 tegra124_overlay_formats[] = { DRM_FORMAT_YUV420, /* YU12 */ DRM_FORMAT_YUV422, /* YU16 */ DRM_FORMAT_YUV444, /* YU24 */ + DRM_FORMAT_YVU420, /* YV12 */ /* semi-planar formats */ DRM_FORMAT_NV12, DRM_FORMAT_NV21, diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c index 6427155ac4fdf..f176badfd922b 100644 --- a/drivers/gpu/drm/tegra/hub.c +++ b/drivers/gpu/drm/tegra/hub.c @@ -51,6 +51,7 @@ static const u32 tegra_shared_plane_formats[] = { DRM_FORMAT_YUYV, DRM_FORMAT_YUV420, DRM_FORMAT_YUV422, + DRM_FORMAT_YVU420, }; static const u64 tegra_shared_plane_modifiers[] = { diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c index 757bc552809fe..0771a6cce8984 100644 --- a/drivers/gpu/drm/tegra/plane.c +++ b/drivers/gpu/drm/tegra/plane.c @@ -433,6 +433,14 @@ int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv) *format = WIN_COLOR_DEPTH_YCbCr420P; break; + case DRM_FORMAT_YVU420: + if (!swap_uv) + return -EINVAL; + + *format = WIN_COLOR_DEPTH_YCbCr420P; + *swap_uv = true; + break; + case DRM_FORMAT_YUV422: *format = WIN_COLOR_DEPTH_YCbCr422P; break; -- 2.54.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-10-20 6:33 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2026-10-18 22:03 [PATCH v2 0/2] drm/tegra: Support YVU420 Aaron Kling via B4 Relay 2026-10-18 22:03 ` [PATCH v2 1/2] drm/tegra: Support swapping chroma planes Aaron Kling via B4 Relay 2026-10-20 5:08 ` Mikko Perttunen 2026-10-20 5:59 ` Aaron Kling 2026-10-20 6:33 ` Mikko Perttunen 2026-10-18 22:03 ` [PATCH v2 2/2] drm/tegra: Support YVU420 Aaron Kling via B4 Relay
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