Re: [RFC net-next v1 2/2] net. phy: dp83tg720: Add randomized polling intervals for unstable link detection

[Oleksij Rempel <o.rempel@pengutronix.de>]

On Wed, Nov 27, 2024 at 06:33:03PM +0100, Heiner Kallweit wrote:
> On 27.11.2024 14:10, Oleksij Rempel wrote:
> > Address the limitations of the DP83TG720 PHY, which cannot reliably detect or
> > report a stable link state. To handle this, the PHY must be periodically reset
> > when the link is down. However, synchronized reset intervals between the PHY
> > and its link partner can result in a deadlock, preventing the link from
> > re-establishing.
> > 
> Out of curiosity: This PHY isn't normally quirky, but completely broken.
> Why would anybody use it?

Is it rhetorical question, or you are really curios? I can answer it, but it
will not be a short one ¯\_(ツ)_/¯

> >  /* MDIO_MMD_VEND2 registers */
> > @@ -355,6 +374,11 @@ static int dp83tg720_read_status(struct phy_device *phydev)
> >  		if (ret)
> >  			return ret;
> > 
> > +		/* The sleep value is based on testing with the DP83TG720S-Q1
> > +		 * PHY. The PHY needs some time to recover from a link loss.
> > +		 */
> What is the issue during this "time to recover"?
> Is errata information available from the vendor?

I didn't found errata documentation for this chip. But there is
"DP83TC81x, DP83TG72x Software Implementation Guide" SNLA404, describing
the need of reset each 100ms and PHY Reset + PHY Initialization
sequences:
https://www.ti.com/lit/an/snla404/snla404.pdf

So far, i was not able to find any justification for this delay, except
it helped to reduce amount of PHY resets. 
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