From: Dave Jiang <dave.jiang@intel.com>
To: Srirangan Madhavan <smadhavan@nvidia.com>,
Alison Schofield <alison.schofield@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v15 07/16] cxl: Share HDM decoder register unpacking
Date: Mon, 26 Oct 2026 15:41:00 -0700 [thread overview]
Message-ID: <a2af3f10-e96d-4283-a378-6da11d4941f1@intel.com> (raw)
In-Reply-To: <20261011021422.3428136-8-smadhavan@nvidia.com>
On 10/10/26 7:14 PM, Srirangan Madhavan wrote:
> Factor common HDM register parsing into cxl_hdm_unpack_decoder().
> Validate range and interleave parameters in locals before publishing the
> decoder configuration, including enable and lock flags. Reject nonzero
> ranges whose end overflows the address space while preserving the
> zero-size range representation.
>
> Read switch target lists and endpoint DPA skip in their respective
> branches of init_hdm_decoder().
>
> Preserve the decoder ID allocated by cxl_decoder_init() when publishing
> the parsed configuration.
>
> Link: https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git/commit/?id=7d6ed7faf7d8e14abce8ae23902d5323738868d2
> Suggested-by: Dave Jiang <dave.jiang@intel.com>
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> Assisted-by: LLM
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/core.h | 3 ++
> drivers/cxl/core/hdm.c | 54 +++++++++-------------------------
> drivers/cxl/core/hdm_regs.c | 58 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 74 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index fb14b222f3ca..d69864b25656 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -147,6 +147,9 @@ void cxl_commit_start_switch(const struct cxl_decoder_config *config,
> u64 targets, void __iomem *hdm);
> int cxld_await_commit(void __iomem *hdm, int id);
>
> +int cxl_hdm_unpack_decoder(struct cxl_decoder_config *config, int id,
> + u32 ctrl, u64 base, u64 size);
> +
> int cxl_memdev_init(void);
> void cxl_memdev_exit(void);
> void cxl_mbox_init(void);
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 47cf49bcd2e5..1a19078e6c6c 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -939,8 +939,8 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> u64 *dpa_base, struct cxl_endpoint_dvsec_info *info)
> {
> struct cxl_endpoint_decoder *cxled = NULL;
> + struct cxl_decoder_config config;
> u64 size, base, skip, dpa_size, lo, hi;
> - bool committed;
> u32 remainder;
> int i, rc;
> u32 ctrl;
> @@ -960,35 +960,24 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> lo = readl(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(which));
> hi = readl(hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(which));
> size = (hi << 32) + lo;
> - committed = !!(ctrl & CXL_HDM_DECODER0_CTRL_COMMITTED);
> + rc = cxl_hdm_unpack_decoder(&config, cxld->config.id, ctrl, base, size);
> + if (rc) {
> + dev_warn(&port->dev,
> + "decoder%d.%d: Invalid decoder configuration (ctrl: %#x): %d\n",
> + port->id, cxld->config.id, ctrl, rc);
> + return rc;
> + }
> +
> cxld->commit = cxl_decoder_commit;
> cxld->reset = cxl_decoder_reset;
> -
> - if (!committed)
> - size = 0;
> - if (base == U64_MAX || size == U64_MAX) {
> - dev_warn(&port->dev, "decoder%d.%d: Invalid resource range\n",
> - port->id, cxld->config.id);
> - return -ENXIO;
> - }
> + cxld->config = config;
> + size = range_len(&cxld->config.hpa_range);
>
> if (info)
> cxled = to_cxl_endpoint_decoder(&cxld->dev);
> - cxld->config.hpa_range = (struct range) {
> - .start = base,
> - .end = base + size - 1,
> - };
>
> /* decoders are enabled if committed */
> - if (committed) {
> - cxld->config.flags |= CXL_DECODER_F_ENABLE;
> - if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK)
> - cxld->config.flags |= CXL_DECODER_F_LOCK;
> - if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl))
> - cxld->config.target_type = CXL_DECODER_HOSTONLYMEM;
> - else
> - cxld->config.target_type = CXL_DECODER_DEVMEM;
> -
> + if (cxld->config.flags & CXL_DECODER_F_ENABLE) {
> guard(rwsem_write)(&cxl_rwsem.region);
> if (cxld->config.id != cxl_num_decoders_committed(port)) {
> dev_warn(&port->dev,
> @@ -1022,23 +1011,6 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which));
> }
> }
> - rc = eiw_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl),
> - &cxld->config.interleave_ways);
> - if (rc) {
> - dev_warn(&port->dev,
> - "decoder%d.%d: Invalid interleave ways (ctrl: %#x)\n",
> - port->id, cxld->config.id, ctrl);
> - return rc;
> - }
> - rc = eig_to_granularity(FIELD_GET(CXL_HDM_DECODER0_CTRL_IG_MASK, ctrl),
> - &cxld->config.interleave_granularity);
> - if (rc) {
> - dev_warn(&port->dev,
> - "decoder%d.%d: Invalid interleave granularity (ctrl: %#x)\n",
> - port->id, cxld->config.id, ctrl);
> - return rc;
> - }
> -
> dev_dbg(&port->dev, "decoder%d.%d: range: %#llx-%#llx iw: %d ig: %d\n",
> port->id, cxld->config.id, cxld->config.hpa_range.start, cxld->config.hpa_range.end,
> cxld->config.interleave_ways, cxld->config.interleave_granularity);
> @@ -1053,7 +1025,7 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> return 0;
> }
>
> - if (!committed)
> + if (!(cxld->config.flags & CXL_DECODER_F_ENABLE))
> return 0;
>
> dpa_size = div_u64_rem(size, cxld->config.interleave_ways, &remainder);
> diff --git a/drivers/cxl/core/hdm_regs.c b/drivers/cxl/core/hdm_regs.c
> index 53d2f236e49c..b6ee4becde8d 100644
> --- a/drivers/cxl/core/hdm_regs.c
> +++ b/drivers/cxl/core/hdm_regs.c
> @@ -116,3 +116,61 @@ void cxl_commit_start_switch(const struct cxl_decoder_config *config,
> writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id));
> }
> EXPORT_SYMBOL_FOR_MODULES(cxl_commit_start_switch, "cxl_core");
> +
> +int cxl_hdm_unpack_decoder(struct cxl_decoder_config *config, int id,
> + u32 ctrl, u64 base, u64 size)
> +{
> + bool committed = FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl);
> + enum cxl_decoder_type target_type = 0;
> + int interleave_granularity;
> + int interleave_ways;
> + unsigned long flags = 0;
> + struct range hpa_range;
> + u64 end;
> + int rc;
> +
> + if (!committed)
> + size = 0;
> + if (base == U64_MAX || size == U64_MAX)
> + return -ENXIO;
> + if (size && check_add_overflow(base, size - 1, &end))
> + return -ENXIO;
> + if (!size)
> + end = base - 1;
> +
> + hpa_range = (struct range) {
> + .start = base,
> + .end = end,
> + };
> +
> + if (committed) {
> + flags |= CXL_DECODER_F_ENABLE;
> + if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK)
> + flags |= CXL_DECODER_F_LOCK;
> + if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl))
> + target_type = CXL_DECODER_HOSTONLYMEM;
> + else
> + target_type = CXL_DECODER_DEVMEM;
> + }
> +
> + rc = eiw_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl),
> + &interleave_ways);
> + if (rc)
> + return rc;
> + rc = eig_to_granularity(FIELD_GET(CXL_HDM_DECODER0_CTRL_IG_MASK, ctrl),
> + &interleave_granularity);
> + if (rc)
> + return rc;
> +
> + *config = (struct cxl_decoder_config) {
> + .id = id,
> + .hpa_range = hpa_range,
> + .interleave_ways = interleave_ways,
> + .interleave_granularity = interleave_granularity,
> + .target_type = target_type,
> + .flags = flags,
> + };
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_FOR_MODULES(cxl_hdm_unpack_decoder, "cxl_core");
next prev parent reply other threads:[~2026-10-26 22:41 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-11 2:14 [PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-27 4:13 ` Alison Schofield
2026-10-11 2:14 ` [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 05/16] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-26 22:20 ` Dave Jiang
2026-10-27 6:23 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 06/16] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-26 22:32 ` Dave Jiang
2026-10-27 6:24 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-26 22:41 ` Dave Jiang [this message]
2026-10-27 6:31 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 08/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-26 22:56 ` Dave Jiang
2026-10-27 6:50 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-27 8:07 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-27 3:25 ` Alison Schofield
2026-10-27 4:32 ` Alison Schofield
2026-10-11 2:14 ` [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-27 3:56 ` Alison Schofield
2026-10-11 2:14 ` [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks Srirangan Madhavan
2026-10-27 2:41 ` Alison Schofield
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