[PATCH 0/2] I2C SCL counter updates for Qualcomm IPQ5424 SoC

[PATCH 0/2] I2C SCL counter updates for Qualcomm IPQ5424 SoC

[Kathiravan Thirumoorthy]

To meet the specification requirement in the standard-mode bus frequency,
update the SCL counters as recommended by the design team.

Also, SCL counters for the FW based SEs are different. Identify if the
SE is mini-core or firmware based and chose the appropriate counter
values.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
Kathiravan Thirumoorthy (2):
      i2c: qcom-geni: update frequency table to fix timing parameters
      i2c: qcom-geni: Add I2C frequency table for firmware-based SEs

 drivers/i2c/busses/i2c-qcom-geni.c | 27 +++++++++++++++++++--------
 include/linux/soc/qcom/geni-se.h   |  1 +
 2 files changed, 20 insertions(+), 8 deletions(-)
---
base-commit: 3d08ff75a47a3e7e2ab45a3bcab6723b4d906422
change-id: 20260808-ipq5424_i2c_scl_updates-f1696a0590fc

Best regards,
--  
Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>

[PATCH 1/2] i2c: qcom-geni: update frequency table to fix timing parameters

[Kathiravan Thirumoorthy]

In IPQ5424, to meet the setup and hold timing requirements in the
standard mode, update the frequency table with the values recommended by
HW design team.

Also remove the stray space in the I2C_MAX_FAST_MODE_FREQ entry.

Cc: <stable@vger.kernel.org>
Fixes: 85c34532849d ("i2c: qcom-geni: fix I2C frequency table to achieve accurate bus rates")
Fixes: 506bb2ab0075 ("i2c: qcom-geni: Support systems with 32MHz serial engine clock")
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
 drivers/i2c/busses/i2c-qcom-geni.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 658636c1ee0e..00013b41a6f5 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -188,8 +188,8 @@ static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = {
 
 /* source_clock = 32 MHz */
 static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = {
-	{ I2C_MAX_STANDARD_MODE_FREQ, 8, 14, 18, 38 },
-	{ I2C_MAX_FAST_MODE_FREQ, 4,  3, 9, 19 },
+	{ I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 },
+	{ I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 },
 	{ I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 },
 	{}
 };

-- 
2.34.1

Re: [PATCH 1/2] i2c: qcom-geni: update frequency table to fix timing parameters

[Mukesh Savaliya]

On 8/11/2026 2:53 PM, Kathiravan Thirumoorthy wrote:
> In IPQ5424, to meet the setup and hold timing requirements in the
> standard mode, update the frequency table with the values recommended by
Changes are fore FAST mode too, please update the commit log accordingly.
> HW design team.
> 
> Also remove the stray space in the I2C_MAX_FAST_MODE_FREQ entry.
> 
> Cc: <stable@vger.kernel.org>
> Fixes: 85c34532849d ("i2c: qcom-geni: fix I2C frequency table to achieve accurate bus rates")
> Fixes: 506bb2ab0075 ("i2c: qcom-geni: Support systems with 32MHz serial engine clock")
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
>   drivers/i2c/busses/i2c-qcom-geni.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
> index 658636c1ee0e..00013b41a6f5 100644
> --- a/drivers/i2c/busses/i2c-qcom-geni.c
> +++ b/drivers/i2c/busses/i2c-qcom-geni.c
> @@ -188,8 +188,8 @@ static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = {
>   
>   /* source_clock = 32 MHz */
>   static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = {
> -	{ I2C_MAX_STANDARD_MODE_FREQ, 8, 14, 18, 38 },
> -	{ I2C_MAX_FAST_MODE_FREQ, 4,  3, 9, 19 },
> +	{ I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 },
> +	{ I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 },
>   	{ I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 },
>   	{}
>   };
> 

Re: [PATCH 1/2] i2c: qcom-geni: update frequency table to fix timing parameters

[Kathiravan Thirumoorthy]

On 8/11/2026 6:12 PM, Mukesh Savaliya wrote:
>
>
> On 8/11/2026 2:53 PM, Kathiravan Thirumoorthy wrote:
>> In IPQ5424, to meet the setup and hold timing requirements in the
>> standard mode, update the frequency table with the values recommended by
> Changes are fore FAST mode too, please update the commit log accordingly.

There are no changes to the FAST mode. As mentioned below, I just 
removed the extra space between values 4 and 3.

>> HW design team.
>>
>> Also remove the stray space in the I2C_MAX_FAST_MODE_FREQ entry.
>>
>> Cc: <stable@vger.kernel.org>
>> Fixes: 85c34532849d ("i2c: qcom-geni: fix I2C frequency table to 
>> achieve accurate bus rates")
>> Fixes: 506bb2ab0075 ("i2c: qcom-geni: Support systems with 32MHz 
>> serial engine clock")
>> Signed-off-by: Kathiravan Thirumoorthy 
>> <kathiravan.thirumoorthy@oss.qualcomm.com>
>> ---
>>   drivers/i2c/busses/i2c-qcom-geni.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c 
>> b/drivers/i2c/busses/i2c-qcom-geni.c
>> index 658636c1ee0e..00013b41a6f5 100644
>> --- a/drivers/i2c/busses/i2c-qcom-geni.c
>> +++ b/drivers/i2c/busses/i2c-qcom-geni.c
>> @@ -188,8 +188,8 @@ static const struct geni_i2c_clk_fld 
>> geni_i2c_clk_map_19p2mhz[] = {
>>     /* source_clock = 32 MHz */
>>   static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = {
>> -    { I2C_MAX_STANDARD_MODE_FREQ, 8, 14, 18, 38 },
>> -    { I2C_MAX_FAST_MODE_FREQ, 4,  3, 9, 19 },
>> +    { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 },
>> +    { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 },
>>       { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 },
>>       {}
>>   };
>>
>

[PATCH 2/2] i2c: qcom-geni: Add I2C frequency table for firmware-based SEs

[Kathiravan Thirumoorthy]

On IPQ5424, RTL-based I2C can be supported by both minicore and firmware
based SEs. For firmware-based SEs, use different SCL settings as
recommended by the design team. Introduce a separate table for the same.

Identify whether the SE is minicore or firmware-based and select the
appropriate frequency table to achieve the desired bus frequencies.

Move geni_i2c_clk_map_idx() from geni_i2c_resources_init() to
geni_i2c_init() to ensure SE_HW_PARAM_2 is accessed only after the
required clocks have been enabled.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
 drivers/i2c/busses/i2c-qcom-geni.c | 23 +++++++++++++++++------
 include/linux/soc/qcom/geni-se.h   |  1 +
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 00013b41a6f5..2f3026602c0c 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -194,12 +194,21 @@ static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = {
 	{}
 };
 
+static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz_fwcore[] = {
+	{ I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 25 },
+	{ I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 18 },
+	{ I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 6, 15, 29 },
+	{}
+};
+
 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
 {
 	const struct geni_i2c_clk_fld *itr;
+	bool is_minicore = FIELD_GET(GEN_USE_MINICORES,
+				     readl_relaxed(gi2c->se.base + SE_HW_PARAM_2));
 
 	if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ)
-		itr = geni_i2c_clk_map_32mhz;
+		itr = is_minicore ? geni_i2c_clk_map_32mhz : geni_i2c_clk_map_32mhz_fwcore;
 	else
 		itr = geni_i2c_clk_map_19p2mhz;
 
@@ -1046,6 +1055,13 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c)
 		return ret;
 	}
 
+	ret = geni_i2c_clk_map_idx(gi2c);
+	if (ret) {
+		return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n",
+				     gi2c->clk_freq_out);
+		goto err;
+	}
+
 	proto = geni_se_read_proto(&gi2c->se);
 	if (proto == GENI_SE_INVALID_PROTO) {
 		ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C);
@@ -1109,11 +1125,6 @@ static int geni_i2c_resources_init(struct geni_se *se)
 	if (ret)
 		return ret;
 
-	ret = geni_i2c_clk_map_idx(gi2c);
-	if (ret)
-		return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n",
-				     gi2c->clk_freq_out);
-
 	return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW,
 				  Bps_to_icc(gi2c->clk_freq_out));
 }
diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h
index 29a53bbc0dd4..7e8c0bb6d674 100644
--- a/include/linux/soc/qcom/geni-se.h
+++ b/include/linux/soc/qcom/geni-se.h
@@ -331,6 +331,7 @@ struct geni_se {
 #define RX_FIFO_DEPTH_SHFT		16
 
 /* SE_HW_PARAM_2 fields */
+#define GEN_USE_MINICORES		BIT(12)
 #define PROG_RAM_DEPTH_MSK		GENMASK(10, 0)
 
 #define HW_VER_MAJOR_MASK		GENMASK(31, 28)

-- 
2.34.1

Re: [PATCH 2/2] i2c: qcom-geni: Add I2C frequency table for firmware-based SEs

[Mukesh Savaliya]

On 8/11/2026 2:53 PM, Kathiravan Thirumoorthy wrote:
> On IPQ5424, RTL-based I2C can be supported by both minicore and firmware
> based SEs. For firmware-based SEs, use different SCL settings as
> recommended by the design team. Introduce a separate table for the same.
> 
> Identify whether the SE is minicore or firmware-based and select the
what is minicore ? Please Make it upstream specific, RTL hardened or 
define minicore first.
> appropriate frequency table to achieve the desired bus frequencies.
> 
> Move geni_i2c_clk_map_idx() from geni_i2c_resources_init() to
> geni_i2c_init() to ensure SE_HW_PARAM_2 is accessed only after the
Reasoning required - why only for 32 MHz ? OR better reasoning for 32Mhz 
support related changes.
> required clocks have been enabled.
> 

I suggest to add 32Mhz support as this is already having 19.2MHz 
support. Subject shows generic frequency support sounding like no 
support present.

> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
>   drivers/i2c/busses/i2c-qcom-geni.c | 23 +++++++++++++++++------
>   include/linux/soc/qcom/geni-se.h   |  1 +
>   2 files changed, 18 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
> index 00013b41a6f5..2f3026602c0c 100644
> --- a/drivers/i2c/busses/i2c-qcom-geni.c
> +++ b/drivers/i2c/busses/i2c-qcom-geni.c
> @@ -194,12 +194,21 @@ static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = {
rename to _minicore ?
>   	{}
>   };
>   
> +static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz_fwcore[] = {
> +	{ I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 25 },
> +	{ I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 18 },
> +	{ I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 6, 15, 29 },
> +	{}
> +};
> +
>   static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
>   {
>   	const struct geni_i2c_clk_fld *itr;
> +	bool is_minicore = FIELD_GET(GEN_USE_MINICORES,
> +				     readl_relaxed(gi2c->se.base + SE_HW_PARAM_2));
>   
>   	if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ)
> -		itr = geni_i2c_clk_map_32mhz;
> +		itr = is_minicore ? geni_i2c_clk_map_32mhz : geni_i2c_clk_map_32mhz_fwcore;
_minicore with above table renamed.
>   	else
>   		itr = geni_i2c_clk_map_19p2mhz;
>   
> @@ -1046,6 +1055,13 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c)
[...]

Re: [PATCH 2/2] i2c: qcom-geni: Add I2C frequency table for firmware-based SEs

[Kathiravan Thirumoorthy]

On 8/11/2026 6:12 PM, Mukesh Savaliya wrote:
>
>
> On 8/11/2026 2:53 PM, Kathiravan Thirumoorthy wrote:
>> On IPQ5424, RTL-based I2C can be supported by both minicore and firmware
>> based SEs. For firmware-based SEs, use different SCL settings as
>> recommended by the design team. Introduce a separate table for the same.
>>
>> Identify whether the SE is minicore or firmware-based and select the
> what is minicore ? Please Make it upstream specific, RTL hardened or 
> define minicore first.

Ack.

>> appropriate frequency table to achieve the desired bus frequencies.
>>
>> Move geni_i2c_clk_map_idx() from geni_i2c_resources_init() to
>> geni_i2c_init() to ensure SE_HW_PARAM_2 is accessed only after the
> Reasoning required - why only for 32 MHz ? OR better reasoning for 
> 32Mhz support related changes.

Ack.

>> required clocks have been enabled.
>>
>
> I suggest to add 32Mhz support as this is already having 19.2MHz 
> support. Subject shows generic frequency support sounding like no 
> support present.

Ack.

>
>> Signed-off-by: Kathiravan Thirumoorthy 
>> <kathiravan.thirumoorthy@oss.qualcomm.com>
>> ---
>>   drivers/i2c/busses/i2c-qcom-geni.c | 23 +++++++++++++++++------
>>   include/linux/soc/qcom/geni-se.h   |  1 +
>>   2 files changed, 18 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c 
>> b/drivers/i2c/busses/i2c-qcom-geni.c
>> index 00013b41a6f5..2f3026602c0c 100644
>> --- a/drivers/i2c/busses/i2c-qcom-geni.c
>> +++ b/drivers/i2c/busses/i2c-qcom-geni.c
>> @@ -194,12 +194,21 @@ static const struct geni_i2c_clk_fld 
>> geni_i2c_clk_map_32mhz[] = {
> rename to _minicore ?

Ack.

>>       {}
>>   };
>>   +static const struct geni_i2c_clk_fld 
>> geni_i2c_clk_map_32mhz_fwcore[] = {
>> +    { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 25 },
>> +    { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 18 },
>> +    { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 6, 15, 29 },
>> +    {}
>> +};
>> +
>>   static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
>>   {
>>       const struct geni_i2c_clk_fld *itr;
>> +    bool is_minicore = FIELD_GET(GEN_USE_MINICORES,
>> +                     readl_relaxed(gi2c->se.base + SE_HW_PARAM_2));
>>         if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ)
>> -        itr = geni_i2c_clk_map_32mhz;
>> +        itr = is_minicore ? geni_i2c_clk_map_32mhz : 
>> geni_i2c_clk_map_32mhz_fwcore;
> _minicore with above table renamed.

Ack.

>>       else
>>           itr = geni_i2c_clk_map_19p2mhz;
>>   @@ -1046,6 +1055,13 @@ static int geni_i2c_init(struct geni_i2c_dev 
>> *gi2c)
> [...]

Re: [PATCH 0/2] I2C SCL counter updates for Qualcomm IPQ5424 SoC

[Mukesh Savaliya]

On 8/11/2026 2:53 PM, Kathiravan Thirumoorthy wrote:
> To meet the specification requirement in the standard-mode bus frequency,
> update the SCL counters as recommended by the design team.
> 
Patches shows that you are adding frequency table for standard and fast, 
for patch#1, and all three modes for patch#2. Please, Correct accordingly.
> Also, SCL counters for the FW based SEs are different. Identify if the
> SE is mini-core or firmware based and chose the appropriate counter
> values.
> 
Little better, select frequency parameters based on SE is is RTL core or 
FW based core.

> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> Kathiravan Thirumoorthy (2):
>        i2c: qcom-geni: update frequency table to fix timing parameters
>        i2c: qcom-geni: Add I2C frequency table for firmware-based SEs
> 
>   drivers/i2c/busses/i2c-qcom-geni.c | 27 +++++++++++++++++++--------
>   include/linux/soc/qcom/geni-se.h   |  1 +
>   2 files changed, 20 insertions(+), 8 deletions(-)
> ---
> base-commit: 3d08ff75a47a3e7e2ab45a3bcab6723b4d906422
> change-id: 20260808-ipq5424_i2c_scl_updates-f1696a0590fc
> 
> Best regards,
> --
> Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> 

Re: [PATCH 0/2] I2C SCL counter updates for Qualcomm IPQ5424 SoC

[Kathiravan Thirumoorthy]

On 8/11/2026 6:11 PM, Mukesh Savaliya wrote:
>
>
> On 8/11/2026 2:53 PM, Kathiravan Thirumoorthy wrote:
>> To meet the specification requirement in the standard-mode bus 
>> frequency,
>> update the SCL counters as recommended by the design team.
>>
> Patches shows that you are adding frequency table for standard and 
> fast, for patch#1, and all three modes for patch#2. Please, Correct 
> accordingly.

Nope. Only for standard freq in patch #1. For FAST mode, it is just a 
stray space removal.

>> Also, SCL counters for the FW based SEs are different. Identify if the
>> SE is mini-core or firmware based and chose the appropriate counter
>> values.
>>
> Little better, select frequency parameters based on SE is is RTL core 
> or FW based core.

Ack.

>
>> Signed-off-by: Kathiravan Thirumoorthy 
>> <kathiravan.thirumoorthy@oss.qualcomm.com>
>> ---
>> Kathiravan Thirumoorthy (2):
>>        i2c: qcom-geni: update frequency table to fix timing parameters
>>        i2c: qcom-geni: Add I2C frequency table for firmware-based SEs
>>
>>   drivers/i2c/busses/i2c-qcom-geni.c | 27 +++++++++++++++++++--------
>>   include/linux/soc/qcom/geni-se.h   |  1 +
>>   2 files changed, 20 insertions(+), 8 deletions(-)
>> ---
>> base-commit: 3d08ff75a47a3e7e2ab45a3bcab6723b4d906422
>> change-id: 20260808-ipq5424_i2c_scl_updates-f1696a0590fc
>>
>> Best regards,
>> -- 
>> Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>>
>