[PATCH v2 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC

[PATCH v2 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

This series enables the SMMU and adds DMA coherency support for the
XGMAC nodes across the affected board device trees.

Patch 1 enables the SMMU for the SoCFPGA board device trees where it
was missing. The SoC uses a different memory-mapped base address for
its peripherals, which requires the SMMU to be active so that the
Secure Device Manager (SDM) can correctly access those regions through
address translation.

Patch 2 adds the dma-coherent property to the XGMAC nodes. The SMMU
is enabled and transactions going through it are cache coherent.
Adding dma-coherent prevents redundant cache flush/invalidate
operations and potential stale data issues.

Changes in v2:
- Move SMMU enable into the base DTSI file instead of individual DTS files
- Move dma-coherent property into the base DTSI file instead of individual DTS files
- Improve commit messages and cover letter descriptions with more context on why the changes are needed

Nazim Amirul (2):
  arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees
  arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

-- 
2.43.7

[PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

Enable the SMMU on the SoCFPGA board device trees where it was
missing. The SoC uses a different memory-mapped base address for
its peripherals, which requires the System Memory Management Unit
(SMMU) to be active so that the Secure Device Manager (SDM) can
correctly access those regions through address translation.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
Changes in v2:
- Move SMMU enable into the base DTSI file instead of individual DTS files

 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index b06c6d5d60ee..64f3739a0c33 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -385,7 +385,7 @@ smmu: iommu@16000000 {
 			interrupt-names = "eventq", "gerror", "priq";
 			dma-coherent;
 			#iommu-cells = <1>;
-			status = "disabled";
+			status = "okay";
 		};
 
 		spi0: spi@10da4000 {
-- 
2.43.7

[PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

The SMMU is enabled and transactions going through it are cache
coherent. Add the dma-coherent property to the XGMAC nodes to prevent
redundant cache flush/invalidate operations and potential stale data
issues.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
Changes in v2:
- Move dma-coherent property into the base DTSI file instead of individual DTS files

 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 64f3739a0c33..bef386cb2fcc 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -577,6 +577,7 @@ gmac0: ethernet@10810000 {
 			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
 			snps,clk-csr = <0>;
 			iommus = <&smmu 1>;
+			dma-coherent;
 			status = "disabled";
 
 			stmmac_axi_emac0_setup: stmmac-axi-config {
@@ -690,6 +691,7 @@ gmac1: ethernet@10820000 {
 			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
 			snps,clk-csr = <0>;
 			iommus = <&smmu 2>;
+			dma-coherent;
 			status = "disabled";
 
 			stmmac_axi_emac1_setup: stmmac-axi-config {
@@ -803,6 +805,7 @@ gmac2: ethernet@10830000 {
 			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
 			snps,clk-csr = <0>;
 			iommus = <&smmu 3>;
+			dma-coherent;
 			status = "disabled";
 
 			stmmac_axi_emac2_setup: stmmac-axi-config {
-- 
2.43.7

Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[Dinh Nguyen]

On 5/15/26 03:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> 
> Enable the SMMU on the SoCFPGA board device trees where it was
> missing. The SoC uses a different memory-mapped base address for
> its peripherals, which requires the System Memory Management Unit
> (SMMU) to be active so that the Secure Device Manager (SDM) can
> correctly access those regions through address translation.
> 
> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> ---
> Changes in v2:
> - Move SMMU enable into the base DTSI file instead of individual DTS files
> 
>   arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index b06c6d5d60ee..64f3739a0c33 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>   			interrupt-names = "eventq", "gerror", "priq";
>   			dma-coherent;
>   			#iommu-cells = <1>;
> -			status = "disabled";
> +			status = "okay";
>   		};
>   
>   		spi0: spi@10da4000 {

Please make it a practice to see what formatting previous commits look 
like on the subsystem you're making changes to. For example, this commit 
header should be something like this:


arm64: dts: socfpga: agilex5: Enable the SMMU

Then in your commit message should not restate your commit header. So 
remove "Enable the SMMU on the SoCFPGA board device trees"

Thanks,
Dinh

Re: [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

[Dinh Nguyen]

On 5/15/26 03:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> 
> The SMMU is enabled and transactions going through it are cache
> coherent. Add the dma-coherent property to the XGMAC nodes to prevent
> redundant cache flush/invalidate operations and potential stale data
> issues.
> 
> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> ---
> Changes in v2:
> - Move dma-coherent property into the base DTSI file instead of individual DTS files
> 
>   arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 64f3739a0c33..bef386cb2fcc 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -577,6 +577,7 @@ gmac0: ethernet@10810000 {
>   			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
>   			snps,clk-csr = <0>;
>   			iommus = <&smmu 1>;
> +			dma-coherent;
>   			status = "disabled";
>   
>   			stmmac_axi_emac0_setup: stmmac-axi-config {
> @@ -690,6 +691,7 @@ gmac1: ethernet@10820000 {
>   			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
>   			snps,clk-csr = <0>;
>   			iommus = <&smmu 2>;
> +			dma-coherent;
>   			status = "disabled";
>   
>   			stmmac_axi_emac1_setup: stmmac-axi-config {
> @@ -803,6 +805,7 @@ gmac2: ethernet@10830000 {
>   			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
>   			snps,clk-csr = <0>;
>   			iommus = <&smmu 3>;
> +			dma-coherent;
>   			status = "disabled";
>   
>   			stmmac_axi_emac2_setup: stmmac-axi-config {

Same comment from patch [1/2].

Also, can you add the dma-coherent to the other IPs using the SMMU as well?

Thanks,
Dinh

Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[Krzysztof Kozlowski]

On 15/05/2026 10:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> 
> Enable the SMMU on the SoCFPGA board device trees where it was
> missing. The SoC uses a different memory-mapped base address for
> its peripherals, which requires the System Memory Management Unit
> (SMMU) to be active so that the Secure Device Manager (SDM) can
> correctly access those regions through address translation.
> 
> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> ---
> Changes in v2:
> - Move SMMU enable into the base DTSI file instead of individual DTS files
> 
>  arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index b06c6d5d60ee..64f3739a0c33 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>  			interrupt-names = "eventq", "gerror", "priq";
>  			dma-coherent;
>  			#iommu-cells = <1>;
> -			status = "disabled";
> +			status = "okay";

Which file disabled it?

Best regards,
Krzysztof

Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[Nazle Asmade, Muhammad Nazim Amirul]

On 30/5/2026 7:11 pm, Krzysztof Kozlowski wrote:
> [You don't often get email from krzk@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> On 15/05/2026 10:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>
>> Enable the SMMU on the SoCFPGA board device trees where it was
>> missing. The SoC uses a different memory-mapped base address for
>> its peripherals, which requires the System Memory Management Unit
>> (SMMU) to be active so that the Secure Device Manager (SDM) can
>> correctly access those regions through address translation.
>>
>> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>> ---
>> Changes in v2:
>> - Move SMMU enable into the base DTSI file instead of individual DTS files
>>
>>   arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> index b06c6d5d60ee..64f3739a0c33 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>>                        interrupt-names = "eventq", "gerror", "priq";
>>                        dma-coherent;
>>                        #iommu-cells = <1>;
>> -                     status = "disabled";
>> +                     status = "okay";
> 
> Which file disabled it?
> 
> Best regards,
> Krzysztof
Hi Dinh, Krzysztof

Thank you for the review and feedback!

Addressing Dinh's comment — the commit header has been updated to follow 
the subsystem naming convention.

Addressing Krzysztof's question — the SMMU was disabled in 
socfpga_agilex5.dtsi itself, where the node is defined with status = 
"disabled". This has been clarified in the updated commit message.

https://lore.kernel.org/all/20260604105020.24782-1-muhammad.nazim.amirul.nazle.asmade@altera.com/
https://lore.kernel.org/all/20260604105020.24782-2-muhammad.nazim.amirul.nazle.asmade@altera.com/
https://lore.kernel.org/all/20260604105020.24782-3-muhammad.nazim.amirul.nazle.asmade@altera.com/

BR,
Nazim

Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[Krzysztof Kozlowski]

On 04/06/2026 12:55, Nazle Asmade, Muhammad Nazim Amirul wrote:
> On 30/5/2026 7:11 pm, Krzysztof Kozlowski wrote:
>> [You don't often get email from krzk@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>
>> On 15/05/2026 10:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>>
>>> Enable the SMMU on the SoCFPGA board device trees where it was
>>> missing. The SoC uses a different memory-mapped base address for
>>> its peripherals, which requires the System Memory Management Unit
>>> (SMMU) to be active so that the Secure Device Manager (SDM) can
>>> correctly access those regions through address translation.
>>>
>>> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>> ---
>>> Changes in v2:
>>> - Move SMMU enable into the base DTSI file instead of individual DTS files
>>>
>>>   arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>>> index b06c6d5d60ee..64f3739a0c33 100644
>>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>>> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>>>                        interrupt-names = "eventq", "gerror", "priq";
>>>                        dma-coherent;
>>>                        #iommu-cells = <1>;
>>> -                     status = "disabled";
>>> +                     status = "okay";
>>
>> Which file disabled it?
>>
>> Best regards,
>> Krzysztof
> Hi Dinh, Krzysztof
> 
> Thank you for the review and feedback!
> 
> Addressing Dinh's comment — the commit header has been updated to follow 
> the subsystem naming convention.
> 
> Addressing Krzysztof's question — the SMMU was disabled in 
> socfpga_agilex5.dtsi itself, where the node is defined with status = 
> "disabled". This has been clarified in the updated commit message.

This makes no sense. I am asking which nod makes it disabled now, that
you need to enable it.

Best regards,
Krzysztof

Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[Nazle Asmade, Muhammad Nazim Amirul]

On 4/6/2026 7:15 pm, Krzysztof Kozlowski wrote:
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index b06c6d5d60ee..64f3739a0c33 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>                         interrupt-names = "eventq", "gerror", "priq";
>                         dma-coherent;
>                         #iommu-cells = <1>;
> -                     status = "disabled";
> +                     status = "okay";
Hi Krzysztof,

The smmu: iommu@16000000 node in socfpga_agilex5.dtsi is defined with 
status = "disabled" as the default. It was not enabled during the 
initial Agilex5 bring-up.

Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[Krzysztof Kozlowski]

On 04/06/2026 14:00, Nazle Asmade, Muhammad Nazim Amirul wrote:
> On 4/6/2026 7:15 pm, Krzysztof Kozlowski wrote:
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> index b06c6d5d60ee..64f3739a0c33 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>>                         interrupt-names = "eventq", "gerror", "priq";
>>                         dma-coherent;
>>                         #iommu-cells = <1>;
>> -                     status = "disabled";
>> +                     status = "okay";
> Hi Krzysztof,
> 
> The smmu: iommu@16000000 node in socfpga_agilex5.dtsi is defined with 

Which file are we discussing here? socfpga_agilex5.dtsi. Then why do you
refer to the same file?

> status = "disabled" as the default. It was not enabled during the 
> initial Agilex5 bring-up.


Best regards,
Krzysztof

Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[Nazle Asmade, Muhammad Nazim Amirul]

On 4/6/2026 8:42 pm, Krzysztof Kozlowski wrote:
> On 04/06/2026 14:00, Nazle Asmade, Muhammad Nazim Amirul wrote:
>> On 4/6/2026 7:15 pm, Krzysztof Kozlowski wrote:
>>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>>> index b06c6d5d60ee..64f3739a0c33 100644
>>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>>> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>>>                          interrupt-names = "eventq", "gerror", "priq";
>>>                          dma-coherent;
>>>                          #iommu-cells = <1>;
>>> -                     status = "disabled";
>>> +                     status = "okay";
>> Hi Krzysztof,
>>
>> The smmu: iommu@16000000 node in socfpga_agilex5.dtsi is defined with
> 
> Which file are we discussing here? socfpga_agilex5.dtsi. Then why do you
> refer to the same file?
> 
>> status = "disabled" as the default. It was not enabled during the
>> initial Agilex5 bring-up.
> 
> 
> Best regards,
> Krzysztof
Hi Krzysztof,

Apologies for the confusion. I was referring to socfpga_agilex5.dtsi 
itself, and I believe that is what you meant as well — we should simply 
remove the status = "disabled" line only, since the default status is 
"okay" when not specified.

BR,
Nazim