From: <Ryan.Wanner@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<alexandre.belloni@bootlin.com>, <claudiu.beznea@tuxon.dev>,
<nicolas.ferre@microchip.com>
Cc: <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<varshini.rajendran@microchip.com>
Subject: [PATCH v4 28/31] clk: at91: at91sam9260: switch to parent_hw and parent_data
Date: Thu, 18 Sep 2025 14:16:10 -0700 [thread overview]
Message-ID: <a85eafe6b462d385c399f8e56773dbedaa1f3260.1758226719.git.Ryan.Wanner@microchip.com> (raw)
In-Reply-To: <cover.1758226719.git.Ryan.Wanner@microchip.com>
From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Switch AT91SAM92600 clocks to use parent_hw and parent_data. Having
parent_hw instead of parent names improves to clock registration
speed and re-parenting.
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
drivers/clk/at91/at91sam9260.c | 120 ++++++++++++++++++---------------
1 file changed, 67 insertions(+), 53 deletions(-)
diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c
index 55350331b07e..2ac2a340da2f 100644
--- a/drivers/clk/at91/at91sam9260.c
+++ b/drivers/clk/at91/at91sam9260.c
@@ -9,7 +9,7 @@
struct sck {
char *n;
- char *p;
+ struct clk_hw *parent_hw;
u8 id;
};
@@ -24,7 +24,7 @@ struct at91sam926x_data {
const struct clk_pll_layout *pllb_layout;
const struct clk_pll_characteristics *pllb_characteristics;
const struct clk_master_characteristics *mck_characteristics;
- const struct sck *sck;
+ struct sck *sck;
const struct pck *pck;
u8 num_sck;
u8 num_pck;
@@ -72,11 +72,11 @@ static const struct clk_pll_characteristics sam9260_pllb_characteristics = {
.out = sam9260_pllb_out,
};
-static const struct sck at91sam9260_systemck[] = {
- { .n = "uhpck", .p = "usbck", .id = 6 },
- { .n = "udpck", .p = "usbck", .id = 7 },
- { .n = "pck0", .p = "prog0", .id = 8 },
- { .n = "pck1", .p = "prog1", .id = 9 },
+static struct sck at91sam9260_systemck[] = {
+ { .n = "uhpck", .id = 6 },
+ { .n = "udpck", .id = 7 },
+ { .n = "pck0", .id = 8 },
+ { .n = "pck1", .id = 9 },
};
static const struct pck at91sam9260_periphck[] = {
@@ -213,15 +213,15 @@ static const struct clk_pll_characteristics sam9261_pllb_characteristics = {
.out = sam9261_pllb_out,
};
-static const struct sck at91sam9261_systemck[] = {
- { .n = "uhpck", .p = "usbck", .id = 6 },
- { .n = "udpck", .p = "usbck", .id = 7 },
- { .n = "pck0", .p = "prog0", .id = 8 },
- { .n = "pck1", .p = "prog1", .id = 9 },
- { .n = "pck2", .p = "prog2", .id = 10 },
- { .n = "pck3", .p = "prog3", .id = 11 },
- { .n = "hclk0", .p = "masterck_div", .id = 16 },
- { .n = "hclk1", .p = "masterck_div", .id = 17 },
+static struct sck at91sam9261_systemck[] = {
+ { .n = "uhpck", .id = 6 },
+ { .n = "udpck", .id = 7 },
+ { .n = "pck0", .id = 8 },
+ { .n = "pck1", .id = 9 },
+ { .n = "pck2", .id = 10 },
+ { .n = "pck3", .id = 11 },
+ { .n = "hclk0", .id = 16 },
+ { .n = "hclk1", .id = 17 },
};
static const struct pck at91sam9261_periphck[] = {
@@ -277,13 +277,13 @@ static const struct clk_pll_characteristics sam9263_pll_characteristics = {
.out = sam9260_plla_out,
};
-static const struct sck at91sam9263_systemck[] = {
- { .n = "uhpck", .p = "usbck", .id = 6 },
- { .n = "udpck", .p = "usbck", .id = 7 },
- { .n = "pck0", .p = "prog0", .id = 8 },
- { .n = "pck1", .p = "prog1", .id = 9 },
- { .n = "pck2", .p = "prog2", .id = 10 },
- { .n = "pck3", .p = "prog3", .id = 11 },
+static struct sck at91sam9263_systemck[] = {
+ { .n = "uhpck", .id = 6 },
+ { .n = "udpck", .id = 7 },
+ { .n = "pck0", .id = 8 },
+ { .n = "pck1", .id = 9 },
+ { .n = "pck2", .id = 10 },
+ { .n = "pck3", .id = 11 },
};
static const struct pck at91sam9263_periphck[] = {
@@ -330,12 +330,11 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
struct at91sam926x_data *data)
{
const char *slowxtal_name, *mainxtal_name;
+ struct clk_parent_data parent_data[4];
struct pmc_data *at91sam9260_pmc;
u32 usb_div[] = { 1, 2, 4, 0 };
- const char *parent_names[6];
- const char *slck_name;
+ struct clk_hw *usbck_hw, *hw;
struct regmap *regmap;
- struct clk_hw *hw;
int i;
bool bypass;
@@ -363,12 +362,13 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
bypass = of_property_read_bool(np, "atmel,osc-bypass");
- hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
+ hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
+ &AT91_CLK_PD_NAME(mainxtal_name),
bypass);
if (IS_ERR(hw))
goto err_free;
- hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL);
+ hw = at91_clk_register_rm9200_main(regmap, "mainck", NULL, &AT91_CLK_PD_HW(hw));
if (IS_ERR(hw))
goto err_free;
@@ -382,20 +382,17 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
if (IS_ERR(hw))
goto err_free;
- parent_names[0] = "slow_rc_osc";
- parent_names[1] = "slow_xtal";
- hw = at91_clk_register_sam9260_slow(regmap, "slck",
- parent_names, NULL, 2);
+ parent_data[0] = AT91_CLK_PD_HW(hw);
+ parent_data[1] = AT91_CLK_PD_NAME(slowxtal_name);
+ hw = at91_clk_register_sam9260_slow(regmap, "slck", NULL, parent_data, 2);
if (IS_ERR(hw))
goto err_free;
at91sam9260_pmc->chws[PMC_SLOW] = hw;
- slck_name = "slck";
- } else {
- slck_name = slowxtal_name;
}
- hw = at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0,
+ hw = at91_clk_register_pll(regmap, "pllack", NULL,
+ &AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]), 0,
data->plla_layout,
data->plla_characteristics);
if (IS_ERR(hw))
@@ -403,7 +400,8 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
at91sam9260_pmc->chws[PMC_PLLACK] = hw;
- hw = at91_clk_register_pll(regmap, "pllbck", "mainck", NULL, 1,
+ hw = at91_clk_register_pll(regmap, "pllbck", NULL,
+ &AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]), 1,
data->pllb_layout,
data->pllb_characteristics);
if (IS_ERR(hw))
@@ -411,12 +409,12 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
at91sam9260_pmc->chws[PMC_PLLBCK] = hw;
- parent_names[0] = slck_name;
- parent_names[1] = "mainck";
- parent_names[2] = "pllack";
- parent_names[3] = "pllbck";
+ parent_data[0] = AT91_CLK_PD_NAME(slowxtal_name);
+ parent_data[1] = AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]);
+ parent_data[2] = AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLACK]);
+ parent_data[3] = AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLACK]);
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
- parent_names, NULL,
+ NULL, parent_data,
&at91rm9200_master_layout,
data->mck_characteristics,
&at91sam9260_mck_lock);
@@ -424,7 +422,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
goto err_free;
hw = at91_clk_register_master_div(regmap, "masterck_div",
- "masterck_pres", NULL,
+ NULL, &AT91_CLK_PD_HW(hw),
&at91rm9200_master_layout,
data->mck_characteristics,
&at91sam9260_mck_lock,
@@ -434,21 +432,23 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
at91sam9260_pmc->chws[PMC_MCK] = hw;
- hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", NULL, usb_div);
- if (IS_ERR(hw))
+ usbck_hw = at91rm9200_clk_register_usb(regmap, "usbck", NULL,
+ &AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLBCK]),
+ usb_div);
+ if (IS_ERR(usbck_hw))
goto err_free;
- parent_names[0] = slck_name;
- parent_names[1] = "mainck";
- parent_names[2] = "pllack";
- parent_names[3] = "pllbck";
+ parent_data[0] = AT91_CLK_PD_NAME(slowxtal_name);
+ parent_data[1] = AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]);
+ parent_data[2] = AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLACK]);
+ parent_data[3] = AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLBCK]);
for (i = 0; i < data->num_progck; i++) {
char name[6];
snprintf(name, sizeof(name), "prog%d", i);
hw = at91_clk_register_programmable(regmap, name,
- parent_names, NULL, 4, i,
+ NULL, parent_data, 4, i,
&at91rm9200_programmable_layout,
NULL);
if (IS_ERR(hw))
@@ -457,9 +457,22 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
at91sam9260_pmc->pchws[i] = hw;
}
+ /* Set systemck parent hws. */
+ data->sck[0].parent_hw = usbck_hw;
+ data->sck[1].parent_hw = usbck_hw;
+ data->sck[2].parent_hw = at91sam9260_pmc->pchws[0];
+ data->sck[3].parent_hw = at91sam9260_pmc->pchws[1];
+ if (data->num_sck == 6) {
+ data->sck[4].parent_hw = at91sam9260_pmc->pchws[2];
+ data->sck[5].parent_hw = at91sam9260_pmc->pchws[3];
+ }
+ if (data->num_sck == 8) {
+ data->sck[6].parent_hw = at91sam9260_pmc->chws[PMC_MCK];
+ data->sck[7].parent_hw = at91sam9260_pmc->chws[PMC_MCK];
+ }
for (i = 0; i < data->num_sck; i++) {
- hw = at91_clk_register_system(regmap, data->sck[i].n,
- data->sck[i].p, NULL,
+ hw = at91_clk_register_system(regmap, data->sck[i].n, NULL,
+ &AT91_CLK_PD_HW(data->sck[i].parent_hw),
data->sck[i].id, 0);
if (IS_ERR(hw))
goto err_free;
@@ -470,7 +483,8 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
for (i = 0; i < data->num_pck; i++) {
hw = at91_clk_register_peripheral(regmap,
data->pck[i].n,
- "masterck_div", NULL,
+ NULL,
+ &AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MCK]),
data->pck[i].id);
if (IS_ERR(hw))
goto err_free;
--
2.43.0
next prev parent reply other threads:[~2025-09-18 21:16 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-18 21:15 [PATCH v4 00/31] clk: at91: add support for parent_data and Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 01/31] clk: at91: pmc: add macros for clk_parent_data Ryan.Wanner
2025-10-20 19:40 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 02/31] clk: at91: pmc: Move macro to header file Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 03/31] clk: at91: sam9x75: switch to parent_hw and parent_data Ryan.Wanner
2025-10-20 19:38 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 04/31] clk: at91: clk-sam9x60-pll: use clk_parent_data Ryan.Wanner
2025-10-20 19:41 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 05/31] clk: at91: clk-peripheral: switch to clk_parent_data Ryan.Wanner
2025-10-20 19:41 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 06/31] clk: at91: clk-main: switch to clk parent data Ryan.Wanner
2025-10-20 19:42 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 07/31] clk: at91: clk-utmi: use clk_parent_data Ryan.Wanner
2025-10-20 19:43 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 08/31] clk: at91: clk-master: " Ryan.Wanner
2025-10-20 19:44 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 09/31] clk: at91: clk-programmable: " Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 10/31] clk: at91: clk-generated: " Ryan.Wanner
2025-10-20 19:39 ` Claudiu Beznea
2025-10-20 19:45 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 11/31] clk: at91: clk-usb: add support for clk_parent_data Ryan.Wanner
2025-10-20 19:17 ` Claudiu Beznea
2025-12-18 16:23 ` Ryan.Wanner
2025-12-23 14:00 ` claudiu beznea
2026-01-05 17:58 ` Ryan.Wanner
2026-01-10 15:03 ` Claudiu Beznea
2026-01-12 21:25 ` Ryan Wanner
2026-01-16 6:57 ` claudiu beznea
2025-09-18 21:15 ` [PATCH v4 12/31] clk: at91: clk-system: use clk_parent_data Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 13/31] clk: at91: sama7d65: switch to parent_hw and parent_data Ryan.Wanner
2025-10-20 19:14 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 14/31] clk: at91: clk-pll: add support for parent_hw Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 15/31] clk: at91: clk-audio-pll: " Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 16/31] clk: at91: clk-plldiv: " Ryan.Wanner
2025-10-20 19:12 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 17/31] clk: at91: clk-h32mx: " Ryan.Wanner
2025-10-20 19:12 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 18/31] clk: at91: clk-i2s-mux: " Ryan.Wanner
2025-10-20 19:13 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 19/31] clk: at91: clk-smd: add support for clk_parent_data Ryan.Wanner
2025-10-20 19:14 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 20/31] clk: at91: clk-slow: add support for parent_hw Ryan.Wanner
2025-10-20 19:17 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 21/31] clk: at91: dt-compat: switch to parent_hw and parent_data Ryan.Wanner
2025-10-20 19:15 ` Claudiu Beznea
2026-01-09 17:03 ` Ryan Wanner
2026-01-10 15:07 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 22/31] clk: at91: sam9x60: " Ryan.Wanner
2025-09-18 21:16 ` [PATCH v4 23/31] clk: at91: sama5d2: " Ryan.Wanner
2025-10-20 19:19 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 24/31] clk: at91: sama5d3: " Ryan.Wanner
2025-09-18 21:16 ` [PATCH v4 25/31] clk: at91: sama5d4: " Ryan.Wanner
2025-09-18 21:16 ` [PATCH v4 26/31] clk: at91: at91sam9x5: " Ryan.Wanner
2025-10-20 19:19 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 27/31] clk: at91: at91rm9200: " Ryan.Wanner
2025-09-18 21:16 ` Ryan.Wanner [this message]
2025-10-20 19:35 ` [PATCH v4 28/31] clk: at91: at91sam9260: " Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 29/31] clk: at91: at91sam9g45: " Ryan.Wanner
2025-09-18 21:16 ` [PATCH v4 30/31] clk: at91: at91sam9n12: " Ryan.Wanner
2025-09-18 21:16 ` [PATCH v4 31/31] clk: at91: at91sam9rl: switch to clk_parent_data Ryan.Wanner
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