Re: [PATCH 1/3] dt-bindings: clock: qcom,sm8450-videocc: Fix clock inputs for Glymur

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 9/29/26 4:08 PM, Shawn Guo wrote:
> On Tue, Sep 29, 2026 at 09:57:40AM +0200, Krzysztof Kozlowski wrote:
>> On Fri, Sep 25, 2026 at 12:11:50AM +0800, Shawn Guo wrote:
>>> The schema describes exactly two clock inputs for every compatible it
>>> covers, a board XO and a video AHB clock from GCC. That is only true
>>> for part of the drivers bound to these compatibles. videocc-glymur.c,
>>> which handles qcom,glymur-videocc and qcom,nord-videocc, and
>>> videocc-sm8750.c both declare their DT inputs as DT_BI_TCXO,
>>> DT_BI_TCXO_AO and DT_SLEEP_CLK, and parent video_cc_sleep_clk_src on
>>> DT_SLEEP_CLK.
>>
>> I don't understand what you are saying here. You are mixing drivers and
>> compatibles.
> 
> You are right! The argument was the wrong way round. What I should have
> written for a schema is the hardware, not the Linux driver.  Sorry about
> that.
> 
> Per the hardware documentation, the video clock controller on Glymur,
> Nord and SM8750 has three clock inputs: the board XO, the always-on board
> XO that feeds its PLL reference, and the 32 kHz chip sleep clock that
> sources its sleep clock generator. There is no AHB clock input
> on the block; the AHB clock the controller uses for itself is generated
> internally from the XO input.

I'm staring at the document and my interpretation of it is that the
AHB clock provides bus access to the controller (via the AHB2AHB
bridge).

Konrad