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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Michal Simek <michal.simek@amd.com>,
	Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>,
	srinivas.kandagatla@linaro.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/5] dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml
Date: Fri, 13 Oct 2023 15:10:28 +0200	[thread overview]
Message-ID: <a990fead-b7af-48e6-ab28-3a69ce07d248@linaro.org> (raw)
In-Reply-To: <edbd1434-c05b-461f-96e5-f57775dcf915@amd.com>

On 13/10/2023 15:06, Michal Simek wrote:
> 
> 
> On 10/13/23 14:54, Krzysztof Kozlowski wrote:
>> On 13/10/2023 14:08, Michal Simek wrote:
>>>
>>>
>>> On 10/13/23 13:58, Krzysztof Kozlowski wrote:
>>>> On 13/10/2023 13:51, Michal Simek wrote:
>>>>>
>>>>>
>>>>> On 10/13/23 13:46, Krzysztof Kozlowski wrote:
>>>>>> On 13/10/2023 13:22, Michal Simek wrote:
>>>>>>>>
>>>>>>>>> +
>>>>>>>>> +required:
>>>>>>>>> +  - compatible
>>>>>>>>
>>>>>>>> required: block goes after patternProperties: block
>>>>>>>>
>>>>>>>>> +
>>>>>>>>> +patternProperties:
>>>>>>>>> +  "^soc_revision@0$":
>>>>>>>>
>>>>>>>> Why do you define individual memory cells? Is this part of a binding?
>>>>>>>> IOW, OS/Linux requires this?
>>>>>>>
>>>>>>> nvmem has in kernel interface where you can reference to nodes. nvmem_cell_get()
>>>>>>> calls. It means you should be able to describe internal layout that's why names
>>>>>>> are used. And address in name is there because of reg property is used to
>>>>>>> describe base offset and size.
>>>>>>
>>>>>> That's not really what I am asking. Why internal layout of memory must
>>>>>> be part of the bindings?
>>>>>
>>>>> It doesn't need to be but offsets are hardcoded inside the driver itself and
>>>>> they can't be different.
>>>>
>>>> Hm, where? I opened drivers/nvmem/zynqmp_nvmem.c and I do not see any
>>>> hard-coded offsets.
>>>
>>> Current driver supports only soc revision from offset 0.
>>> But if you look at 5/5 you need to define offsets where information is present.
>>> +#define SOC_VERSION_OFFSET	0x0
>>> +#define EFUSE_START_OFFSET	0xC
>>> +#define EFUSE_END_OFFSET	0xFC
>>> +#define EFUSE_PUF_START_OFFSET	0x100
>>> +#define EFUSE_PUF_MID_OFFSET	0x140
>>> +#define EFUSE_PUF_END_OFFSET	0x17F
>>
>> There is nothing like this in existing driver, so the argument that "I
>> am adding this to the binding during conversion because driver needs it"
>> is not true. Conversion is only a conversion.
> 
> Conversion in 2/5 is adding only soc revision which is already there. It is 
> starting from 0 and world size is 1. And 0 is not listed because that's start 
> all the time.
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/nvmem/zynqmp_nvmem.c?h=v6.6-rc5#n39

This defines the nvmem config, not what should be where.

> 
> And soc revision was also listed in origin binding example.

Example is not a binding. Please drop enforcement of some specific nodes
from the binding.

> 
>> Now, if you want to add something new to the binding because of new
>> driver changes, that's separate topic.
> 
> Functionality in firmware is there for quite a long time but as I said I am fine 
> if map is not going to be inside dt binding spec.
> 
>> And since it is new change in the driver I can comment: please don't.
>> Your nvmem driver should not depend on it. nvmem is only the provider.
> 
> Let's see what Srinivas says about implementation. If driver should be just 
> provider then pretty much current driver should be completely rewritten to 
> different style. I mean to have just transport via SMCs with offset/size and 
> then providing functionality in firmware.

Best regards,
Krzysztof


  reply	other threads:[~2023-10-13 13:10 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-13 10:14 [PATCH 0/5] Add ZynqMP efuse access support Praveen Teja Kundanala
2023-10-13 10:14 ` [PATCH 1/5] firmware: xilinx: Add ZynqMP efuse access API Praveen Teja Kundanala
2023-10-13 10:14 ` [PATCH 2/5] dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml Praveen Teja Kundanala
2023-10-13 10:30   ` Krzysztof Kozlowski
2023-10-13 11:22     ` Michal Simek
2023-10-13 11:46       ` Krzysztof Kozlowski
2023-10-13 11:51         ` Michal Simek
2023-10-13 11:58           ` Krzysztof Kozlowski
2023-10-13 12:08             ` Michal Simek
2023-10-13 12:54               ` Krzysztof Kozlowski
2023-10-13 13:06                 ` Michal Simek
2023-10-13 13:10                   ` Krzysztof Kozlowski [this message]
2023-10-13 13:12                     ` Michal Simek
2023-10-16  8:01                     ` Michal Simek
2023-10-16 10:06                       ` Kundanala, Praveen Teja
2023-10-13 11:09   ` Rob Herring
2023-10-13 16:23   ` Rob Herring
2023-10-13 10:14 ` [PATCH 3/5] dt-bindings: nvmem: Add nodes for ZynqMP efuses Praveen Teja Kundanala
2023-10-13 10:31   ` Krzysztof Kozlowski
2023-10-13 10:14 ` [PATCH 4/5] arm64: zynqmp: Add ZynqnMP nvmem nodes Praveen Teja Kundanala
2023-10-13 10:32   ` Krzysztof Kozlowski
2023-10-13 11:18     ` Michal Simek
2023-10-13 10:14 ` [PATCH 5/5] nvmem: zynqmp_nvmem: Add support to access efuse Praveen Teja Kundanala

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