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From: Mark Rutland <mark.rutland@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Ryan Roberts <ryan.roberts@arm.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/6] arm64/mm: Ensure correct 48 bit PA gets into TTBRx_EL1
Date: Tue, 4 Nov 2025 15:17:33 +0000	[thread overview]
Message-ID: <aQoZDbuBJ_2YcsyP@J2N7QTR9R3.cambridge.arm.com> (raw)
In-Reply-To: <20251103052618.586763-5-anshuman.khandual@arm.com>

On Mon, Nov 03, 2025 at 05:26:16AM +0000, Anshuman Khandual wrote:
> Even though 48 bit PA representation in TTBRx_EL1 does not involve shifting
> partial bits like 52 bit variant does, they sill need to be masked properly
> for correctness. Hence mask 48 bit PA with TTBRx_EL1_BADDR_MASK.

There is no need for the address "to be masked properly for
correctness".

We added masking for 52-bit PAs due to the need to shuffle the bits
around. There is no need for that when using 48-bit PAs, since the
address must be below 2^48, and the address must be suitably aligned.

If any bits are set outside of this mask, that is a bug in the caller.

Mark.

> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  arch/arm64/include/asm/assembler.h | 1 +
>  arch/arm64/include/asm/pgtable.h   | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
> index 23be85d93348..d5eb09fc5f8a 100644
> --- a/arch/arm64/include/asm/assembler.h
> +++ b/arch/arm64/include/asm/assembler.h
> @@ -609,6 +609,7 @@ alternative_endif
>  	and	\ttbr, \ttbr, #TTBR_BADDR_MASK_52
>  #else
>  	mov	\ttbr, \phys
> +	and	\ttbr, \ttbr, #TTBRx_EL1_BADDR_MASK
>  #endif
>  	.endm
>  
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index 0944e296dd4a..c3110040c137 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -1604,7 +1604,7 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf,
>  #ifdef CONFIG_ARM64_PA_BITS_52
>  #define phys_to_ttbr(addr)	(((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
>  #else
> -#define phys_to_ttbr(addr)	(addr)
> +#define phys_to_ttbr(addr)	(addr & TTBRx_EL1_BADDR_MASK)
>  #endif
>  
>  /*
> -- 
> 2.30.2
> 

  reply	other threads:[~2025-11-04 15:17 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-03  5:26 [PATCH 0/6] arm64/mm: TTBRx_EL1 related changes Anshuman Khandual
2025-11-03  5:26 ` [PATCH 1/6] arm64/mm: Directly use TTBRx_EL1_ASID_MASK Anshuman Khandual
2025-11-03  5:26 ` [PATCH 2/6] arm64/mm: Directly use TTBRx_EL1_CnP Anshuman Khandual
2025-11-03  5:26 ` [PATCH 3/6] arm64/mm: Represent TTBR_BADDR_MASK_52 with TTBRx_EL1_BADDR_MASK Anshuman Khandual
2025-11-03  5:26 ` [PATCH 4/6] arm64/mm: Ensure correct 48 bit PA gets into TTBRx_EL1 Anshuman Khandual
2025-11-04 15:17   ` Mark Rutland [this message]
2025-11-05  3:35     ` Anshuman Khandual
2025-11-03  5:26 ` [PATCH 5/6] arm64/mm: Describe 52 PA folding " Anshuman Khandual
2025-11-03  5:26 ` [PATCH 6/6] arm64/mm: Describe TTBR1_BADDR_4852_OFFSET Anshuman Khandual
2025-11-13  9:18 ` [PATCH 0/6] arm64/mm: TTBRx_EL1 related changes Anshuman Khandual
2025-11-14  9:55   ` Mark Rutland
2025-11-19  1:07     ` Anshuman Khandual

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