* [PATCH 1/3] dt-bindings: display: msm: document DSI controller and phy on QCS8300
2025-09-25 5:35 [PATCH 0/3] Add DSI display support for QCS8300 target Ayushi Makhija
@ 2025-09-25 5:36 ` Ayushi Makhija
2025-09-25 21:59 ` Dmitry Baryshkov
2025-09-25 5:36 ` [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes Ayushi Makhija
2025-09-25 5:36 ` [PATCH 3/3] arm64: dts: qcom: qcs8300-ride: add anx7625 DSI to DP bridge node Ayushi Makhija
2 siblings, 1 reply; 14+ messages in thread
From: Ayushi Makhija @ 2025-09-25 5:36 UTC (permalink / raw)
To: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
Cc: Ayushi Makhija, robdclark, dmitry.baryshkov, sean,
marijn.suijten, andersson, robh, robh+dt, krzk+dt, konradybcio,
conor+dt, andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart,
jonas, jernej.skrabec, quic_rajeevny, quic_vproddut,
quic_jesszhan
Document DSI controller and phy on QCS8300 platform.
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
---
.../display/msm/qcom,qcs8300-mdss.yaml | 100 +++++++++++++++++-
1 file changed, 99 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
index e96baaae9ba9..f34823ed4433 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
@@ -53,13 +53,23 @@ patternProperties:
contains:
const: qcom,qcs8300-dp
+ "^dsi@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ contains:
+ const: qcom,sa8775p-dsi-ctrl
+
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
- const: qcom,qcs8300-edp-phy
+ enum:
+ - qcom,qcs8300-edp-phy
+ - qcom,sa8775p-dsi-phy-5nm
required:
- compatible
@@ -71,6 +81,7 @@ examples:
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
@@ -142,6 +153,14 @@ examples:
remote-endpoint = <&mdss_dp0_in>;
};
};
+
+ port@1 {
+ reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
};
mdp_opp_table: opp-table {
@@ -169,6 +188,85 @@ examples:
};
};
+ dsi@ae94000 {
+ compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+ phys = <&mdss_dsi0_phy>;
+
+ operating-points-v2 = <&dsi0_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ vdda-supply = <&vreg_l5a>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss0_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss0_dsi0_out: endpoint { };
+ };
+ };
+
+ dsi0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94900 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ vdds-supply = <&vreg_l4a>;
+ };
+
mdss_dp0_phy: phy@aec2a00 {
compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
--
2.34.1
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 1/3] dt-bindings: display: msm: document DSI controller and phy on QCS8300
2025-09-25 5:36 ` [PATCH 1/3] dt-bindings: display: msm: document DSI controller and phy on QCS8300 Ayushi Makhija
@ 2025-09-25 21:59 ` Dmitry Baryshkov
0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 21:59 UTC (permalink / raw)
To: Ayushi Makhija
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
robdclark, sean, marijn.suijten, andersson, robh, robh+dt,
krzk+dt, konradybcio, conor+dt, andrzej.hajda, neil.armstrong,
rfoss, Laurent.pinchart, jonas, jernej.skrabec, quic_rajeevny,
quic_vproddut, quic_jesszhan
On Thu, Sep 25, 2025 at 11:06:00AM +0530, Ayushi Makhija wrote:
> Document DSI controller and phy on QCS8300 platform.
>
> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
> ---
> .../display/msm/qcom,qcs8300-mdss.yaml | 100 +++++++++++++++++-
> 1 file changed, 99 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
> index e96baaae9ba9..f34823ed4433 100644
> --- a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
> @@ -53,13 +53,23 @@ patternProperties:
> contains:
> const: qcom,qcs8300-dp
>
> + "^dsi@[0-9a-f]+$":
> + type: object
> + additionalProperties: true
> + properties:
> + compatible:
> + contains:
> + const: qcom,sa8775p-dsi-ctrl
Why? It should be qcs8300-dsi-ctrl
> +
> "^phy@[0-9a-f]+$":
> type: object
> additionalProperties: true
> properties:
> compatible:
> contains:
> - const: qcom,qcs8300-edp-phy
> + enum:
> + - qcom,qcs8300-edp-phy
> + - qcom,sa8775p-dsi-phy-5nm
>
> required:
> - compatible
> @@ -71,6 +81,7 @@ examples:
> #include <dt-bindings/interconnect/qcom,icc.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
> #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
> #include <dt-bindings/power/qcom,rpmhpd.h>
> @@ -142,6 +153,14 @@ examples:
> remote-endpoint = <&mdss_dp0_in>;
> };
> };
> +
> + port@1 {
> + reg = <1>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&mdss_dsi0_in>;
> + };
> + };
> +
Drop extra empty line
> };
>
> mdp_opp_table: opp-table {
> @@ -169,6 +188,85 @@ examples:
> };
> };
>
> + dsi@ae94000 {
> + compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
> + reg = <0x0ae94000 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
> + phys = <&mdss_dsi0_phy>;
> +
> + operating-points-v2 = <&dsi0_opp_table>;
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + vdda-supply = <&vreg_l5a>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss0_dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + mdss0_dsi0_out: endpoint { };
> + };
> + };
> +
> + dsi0_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-358000000 {
> + opp-hz = /bits/ 64 <358000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> + };
> +
> + mdss_dsi0_phy: phy@ae94400 {
> + compatible = "qcom,sa8775p-dsi-phy-5nm";
> + reg = <0x0ae94400 0x200>,
> + <0x0ae94600 0x280>,
> + <0x0ae94900 0x27c>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + vdds-supply = <&vreg_l4a>;
> + };
Wrong indentation
> +
> mdss_dp0_phy: phy@aec2a00 {
> compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes
2025-09-25 5:35 [PATCH 0/3] Add DSI display support for QCS8300 target Ayushi Makhija
2025-09-25 5:36 ` [PATCH 1/3] dt-bindings: display: msm: document DSI controller and phy on QCS8300 Ayushi Makhija
@ 2025-09-25 5:36 ` Ayushi Makhija
2025-09-25 22:02 ` Dmitry Baryshkov
2025-09-25 5:36 ` [PATCH 3/3] arm64: dts: qcom: qcs8300-ride: add anx7625 DSI to DP bridge node Ayushi Makhija
2 siblings, 1 reply; 14+ messages in thread
From: Ayushi Makhija @ 2025-09-25 5:36 UTC (permalink / raw)
To: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
Cc: Ayushi Makhija, robdclark, dmitry.baryshkov, sean,
marijn.suijten, andersson, robh, robh+dt, krzk+dt, konradybcio,
conor+dt, andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart,
jonas, jernej.skrabec, quic_rajeevny, quic_vproddut,
quic_jesszhan
Add device tree nodes for the DSI0 controller with their corresponding
PHY found on Qualcomm QCS8300 SoC.
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 95 ++++++++++++++++++++++++++-
1 file changed, 94 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index e0e1f63fc45b..834ae0522f2f 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
@@ -4854,6 +4855,13 @@ dpu_intf0_out: endpoint {
remote-endpoint = <&mdss_dp0_in>;
};
};
+
+ port@1 {
+ reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
};
mdp_opp_table: opp-table {
@@ -4881,6 +4889,89 @@ opp-650000000 {
};
};
+ mdss_dsi0: dsi@ae94000 {
+ compatible = "qcom,sa8775p-dsi-ctrl","qcom,mdss-dsi-ctrl";
+ reg = <0x0 0x0ae94000 0x0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+ phys = <&mdss_dsi0_phy>;
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0x0 0x0ae94400 0x0 0x200>,
+ <0x0 0x0ae94600 0x0 0x280>,
+ <0x0 0x0ae94900 0x0 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
mdss_dp0_phy: phy@aec2a00 {
compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
@@ -5008,7 +5099,9 @@ dispcc: clock-controller@af00000 {
<&mdss_dp0_phy 0>,
<&mdss_dp0_phy 1>,
<0>, <0>,
- <0>, <0>, <0>, <0>;
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <0>, <0>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.34.1
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes
2025-09-25 5:36 ` [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes Ayushi Makhija
@ 2025-09-25 22:02 ` Dmitry Baryshkov
2025-09-26 9:25 ` Ayushi Makhija
2025-10-05 16:48 ` Ayushi Makhija
0 siblings, 2 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 22:02 UTC (permalink / raw)
To: Ayushi Makhija
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
robdclark, sean, marijn.suijten, andersson, robh, robh+dt,
krzk+dt, konradybcio, conor+dt, andrzej.hajda, neil.armstrong,
rfoss, Laurent.pinchart, jonas, jernej.skrabec, quic_rajeevny,
quic_vproddut, quic_jesszhan
On Thu, Sep 25, 2025 at 11:06:01AM +0530, Ayushi Makhija wrote:
> Add device tree nodes for the DSI0 controller with their corresponding
> PHY found on Qualcomm QCS8300 SoC.
>
> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 95 ++++++++++++++++++++++++++-
> 1 file changed, 94 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index e0e1f63fc45b..834ae0522f2f 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
> #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
> @@ -4854,6 +4855,13 @@ dpu_intf0_out: endpoint {
> remote-endpoint = <&mdss_dp0_in>;
> };
> };
> +
> + port@1 {
> + reg = <1>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&mdss_dsi0_in>;
> + };
> + };
> };
>
> mdp_opp_table: opp-table {
> @@ -4881,6 +4889,89 @@ opp-650000000 {
> };
> };
>
> + mdss_dsi0: dsi@ae94000 {
> + compatible = "qcom,sa8775p-dsi-ctrl","qcom,mdss-dsi-ctrl";
qcom,qcs8300-dsi-ctrl. You might use three compatibles (qcs8300, sa8775p
and the generic one), but there should be qcs8300 one.
Also please add a whitespace after comma or (even better), keep one
compat per line (align on opening quote).
> + reg = <0x0 0x0ae94000 0x0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
> + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
> +
> + phys = <&mdss_dsi0_phy>;
> +
> + operating-points-v2 = <&mdss_dsi_opp_table>;
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss_dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + mdss_dsi0_out: endpoint {
> + };
> + };
> + };
> +
> + mdss_dsi_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-358000000 {
> + opp-hz = /bits/ 64 <358000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> + };
> +
> + mdss_dsi0_phy: phy@ae94400 {
> + compatible = "qcom,sa8775p-dsi-phy-5nm";
Add qcs8300-specific compatible and use sa8775p as a fallback
> + reg = <0x0 0x0ae94400 0x0 0x200>,
> + <0x0 0x0ae94600 0x0 0x280>,
> + <0x0 0x0ae94900 0x0 0x27c>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> + };
> +
> mdss_dp0_phy: phy@aec2a00 {
> compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
>
> @@ -5008,7 +5099,9 @@ dispcc: clock-controller@af00000 {
> <&mdss_dp0_phy 0>,
> <&mdss_dp0_phy 1>,
> <0>, <0>,
> - <0>, <0>, <0>, <0>;
> + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
> + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
> + <0>, <0>;
> power-domains = <&rpmhpd RPMHPD_MMCX>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes
2025-09-25 22:02 ` Dmitry Baryshkov
@ 2025-09-26 9:25 ` Ayushi Makhija
2025-09-26 10:45 ` Konrad Dybcio
2025-09-26 14:05 ` Dmitry Baryshkov
2025-10-05 16:48 ` Ayushi Makhija
1 sibling, 2 replies; 14+ messages in thread
From: Ayushi Makhija @ 2025-09-26 9:25 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
robdclark, sean, marijn.suijten, andersson, robh, robh+dt,
krzk+dt, konradybcio, conor+dt, andrzej.hajda, neil.armstrong,
rfoss, Laurent.pinchart, jonas, jernej.skrabec, quic_rajeevny,
quic_vproddut, quic_jesszhan
On 9/26/2025 3:32 AM, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 11:06:01AM +0530, Ayushi Makhija wrote:
>> Add device tree nodes for the DSI0 controller with their corresponding
>> PHY found on Qualcomm QCS8300 SoC.
>>
>> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 95 ++++++++++++++++++++++++++-
>> 1 file changed, 94 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> index e0e1f63fc45b..834ae0522f2f 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> @@ -3,6 +3,7 @@
>> * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> */
>>
>> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
>> #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
>> #include <dt-bindings/clock/qcom,rpmh.h>
>> #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
>> @@ -4854,6 +4855,13 @@ dpu_intf0_out: endpoint {
>> remote-endpoint = <&mdss_dp0_in>;
>> };
>> };
>> +
>> + port@1 {
>> + reg = <1>;
>> + dpu_intf1_out: endpoint {
>> + remote-endpoint = <&mdss_dsi0_in>;
>> + };
>> + };
>> };
>>
>> mdp_opp_table: opp-table {
>> @@ -4881,6 +4889,89 @@ opp-650000000 {
>> };
>> };
>>
>> + mdss_dsi0: dsi@ae94000 {
>> + compatible = "qcom,sa8775p-dsi-ctrl","qcom,mdss-dsi-ctrl";
>
> qcom,qcs8300-dsi-ctrl. You might use three compatibles (qcs8300, sa8775p
> and the generic one), but there should be qcs8300 one.
>
> Also please add a whitespace after comma or (even better), keep one
> compat per line (align on opening quote).
>
>> + reg = <0x0 0x0ae94000 0x0 0x400>;
>> + reg-names = "dsi_ctrl";
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <4>;
>> +
>> + clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
>> + <&gcc GCC_DISP_HF_AXI_CLK>;
>> + clock-names = "byte",
>> + "byte_intf",
>> + "pixel",
>> + "core",
>> + "iface",
>> + "bus";
>> +
>> + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
>> + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
>> + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
>> + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
>> +
>> + phys = <&mdss_dsi0_phy>;
>> +
>> + operating-points-v2 = <&mdss_dsi_opp_table>;
>> + power-domains = <&rpmhpd RPMHPD_MMCX>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + mdss_dsi0_in: endpoint {
>> + remote-endpoint = <&dpu_intf1_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + mdss_dsi0_out: endpoint {
>> + };
>> + };
>> + };
>> +
>> + mdss_dsi_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-358000000 {
>> + opp-hz = /bits/ 64 <358000000>;
>> + required-opps = <&rpmhpd_opp_svs_l1>;
>> + };
>> + };
>> + };
>> +
>> + mdss_dsi0_phy: phy@ae94400 {
>> + compatible = "qcom,sa8775p-dsi-phy-5nm";
>
> Add qcs8300-specific compatible and use sa8775p as a fallback
>
Hi Dmitry,
I have one doubt, even though the ctrl and phy versions for sa8775p(LeMans) and qcs8300(Monaco) are same.
Why can't we use the same compatible string that we have used for LeMans ctrl and phy ? what is the need to define a separate
compatible string for monaco ctrl and phy ?
Thanks,
Ayushi
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes
2025-09-26 9:25 ` Ayushi Makhija
@ 2025-09-26 10:45 ` Konrad Dybcio
2025-09-26 14:05 ` Dmitry Baryshkov
1 sibling, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2025-09-26 10:45 UTC (permalink / raw)
To: Ayushi Makhija, Dmitry Baryshkov
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
robdclark, sean, marijn.suijten, andersson, robh, robh+dt,
krzk+dt, konradybcio, conor+dt, andrzej.hajda, neil.armstrong,
rfoss, Laurent.pinchart, jonas, jernej.skrabec, quic_rajeevny,
quic_vproddut, quic_jesszhan
On 9/26/25 11:25 AM, Ayushi Makhija wrote:
> On 9/26/2025 3:32 AM, Dmitry Baryshkov wrote:
>> On Thu, Sep 25, 2025 at 11:06:01AM +0530, Ayushi Makhija wrote:
>>> Add device tree nodes for the DSI0 controller with their corresponding
>>> PHY found on Qualcomm QCS8300 SoC.
>>>
>>> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
>>> ---
[...]
>>> + mdss_dsi0_phy: phy@ae94400 {
>>> + compatible = "qcom,sa8775p-dsi-phy-5nm";
>>
>> Add qcs8300-specific compatible and use sa8775p as a fallback
>>
>
> Hi Dmitry,
>
> I have one doubt, even though the ctrl and phy versions for sa8775p(LeMans) and qcs8300(Monaco) are same.
> Why can't we use the same compatible string that we have used for LeMans ctrl and phy ? what is the need to define a separate
> compatible string for monaco ctrl and phy ?
Because they're different SoCs and if it turns out there's e.g.
a silicon bug specific to monaco, we can apply a quirk to just
monaco this way
Konrad
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes
2025-09-26 9:25 ` Ayushi Makhija
2025-09-26 10:45 ` Konrad Dybcio
@ 2025-09-26 14:05 ` Dmitry Baryshkov
2025-09-29 6:37 ` Ayushi Makhija
1 sibling, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2025-09-26 14:05 UTC (permalink / raw)
To: Ayushi Makhija
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
robdclark, sean, marijn.suijten, andersson, robh, robh+dt,
krzk+dt, konradybcio, conor+dt, andrzej.hajda, neil.armstrong,
rfoss, Laurent.pinchart, jonas, jernej.skrabec, quic_rajeevny,
quic_vproddut, quic_jesszhan
On Fri, Sep 26, 2025 at 02:55:19PM +0530, Ayushi Makhija wrote:
> On 9/26/2025 3:32 AM, Dmitry Baryshkov wrote:
> > On Thu, Sep 25, 2025 at 11:06:01AM +0530, Ayushi Makhija wrote:
> >> Add device tree nodes for the DSI0 controller with their corresponding
> >> PHY found on Qualcomm QCS8300 SoC.
> >>
> >> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
> >> ---
> >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 95 ++++++++++++++++++++++++++-
> >> 1 file changed, 94 insertions(+), 1 deletion(-)
> >>
> >> +
> >> + mdss_dsi0_phy: phy@ae94400 {
> >> + compatible = "qcom,sa8775p-dsi-phy-5nm";
> >
> > Add qcs8300-specific compatible and use sa8775p as a fallback
> >
>
> Hi Dmitry,
>
> I have one doubt, even though the ctrl and phy versions for sa8775p(LeMans) and qcs8300(Monaco) are same.
> Why can't we use the same compatible string that we have used for LeMans ctrl and phy ? what is the need to define a separate
> compatible string for monaco ctrl and phy ?
Konrad responded with the reason. But also, this question should have
been asked when you took a first look at the qcom,qcs8300-mdss.yaml.
It has two compats for DPU, DP and eDP PHY blocks (for exactly the same
reason).
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes
2025-09-26 14:05 ` Dmitry Baryshkov
@ 2025-09-29 6:37 ` Ayushi Makhija
0 siblings, 0 replies; 14+ messages in thread
From: Ayushi Makhija @ 2025-09-29 6:37 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
robdclark, sean, marijn.suijten, andersson, robh, robh+dt,
krzk+dt, konradybcio, conor+dt, andrzej.hajda, neil.armstrong,
rfoss, Laurent.pinchart, jonas, jernej.skrabec, quic_rajeevny,
quic_vproddut, quic_jesszhan
On 9/26/2025 7:35 PM, Dmitry Baryshkov wrote:
> On Fri, Sep 26, 2025 at 02:55:19PM +0530, Ayushi Makhija wrote:
>> On 9/26/2025 3:32 AM, Dmitry Baryshkov wrote:
>>> On Thu, Sep 25, 2025 at 11:06:01AM +0530, Ayushi Makhija wrote:
>>>> Add device tree nodes for the DSI0 controller with their corresponding
>>>> PHY found on Qualcomm QCS8300 SoC.
>>>>
>>>> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 95 ++++++++++++++++++++++++++-
>>>> 1 file changed, 94 insertions(+), 1 deletion(-)
>>>>
>>>> +
>>>> + mdss_dsi0_phy: phy@ae94400 {
>>>> + compatible = "qcom,sa8775p-dsi-phy-5nm";
>>>
>>> Add qcs8300-specific compatible and use sa8775p as a fallback
>>>
>>
>> Hi Dmitry,
>>
>> I have one doubt, even though the ctrl and phy versions for sa8775p(LeMans) and qcs8300(Monaco) are same.
>> Why can't we use the same compatible string that we have used for LeMans ctrl and phy ? what is the need to define a separate
>> compatible string for monaco ctrl and phy ?
>
> Konrad responded with the reason. But also, this question should have
> been asked when you took a first look at the qcom,qcs8300-mdss.yaml.
> It has two compats for DPU, DP and eDP PHY blocks (for exactly the same
> reason).
>
Hi Dmitry/Konard,
The previous explanation regarding the use of two compatible strings for DPU/DP was unclear, but it is now well understood. Thanks, for the clarification.
Thanks,
Ayushi
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes
2025-09-25 22:02 ` Dmitry Baryshkov
2025-09-26 9:25 ` Ayushi Makhija
@ 2025-10-05 16:48 ` Ayushi Makhija
2025-10-05 22:01 ` Dmitry Baryshkov
1 sibling, 1 reply; 14+ messages in thread
From: Ayushi Makhija @ 2025-10-05 16:48 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
robdclark, sean, marijn.suijten, andersson, robh, robh+dt,
krzk+dt, konradybcio, conor+dt, andrzej.hajda, neil.armstrong,
rfoss, Laurent.pinchart, jonas, jernej.skrabec, quic_rajeevny,
quic_vproddut, quic_jesszhan
On 9/26/2025 3:32 AM, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 11:06:01AM +0530, Ayushi Makhija wrote:
>> Add device tree nodes for the DSI0 controller with their corresponding
>> PHY found on Qualcomm QCS8300 SoC.
>>
>> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 95 ++++++++++++++++++++++++++-
>> 1 file changed, 94 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> index e0e1f63fc45b..834ae0522f2f 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> @@ -3,6 +3,7 @@
>> * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> */
>>
>> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
>> #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
>> #include <dt-bindings/clock/qcom,rpmh.h>
>> #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
>> @@ -4854,6 +4855,13 @@ dpu_intf0_out: endpoint {
>> remote-endpoint = <&mdss_dp0_in>;
>> };
>> };
>> +
>> + port@1 {
>> + reg = <1>;
>> + dpu_intf1_out: endpoint {
>> + remote-endpoint = <&mdss_dsi0_in>;
>> + };
>> + };
>> };
>>
>> mdp_opp_table: opp-table {
>> @@ -4881,6 +4889,89 @@ opp-650000000 {
>> };
>> };
>>
>> + mdss_dsi0: dsi@ae94000 {
>> + compatible = "qcom,sa8775p-dsi-ctrl","qcom,mdss-dsi-ctrl";
>
> qcom,qcs8300-dsi-ctrl. You might use three compatibles (qcs8300, sa8775p
> and the generic one), but there should be qcs8300 one.
>
Hi Dmitry,
If I am adding three compatible string for ctrl,
compatible = "qcom,qcs8300-dsi-ctrl",
"qcom,sa8775p-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
while validating dt-binding and dtsi against dt-schema. I am getting below errors
/local/mnt/workspace/amakhija/linux_next/linux/arch/arm64/boot/dts/qcom/qcs8300-ride.dtb: dsi@ae94000: compatible: 'oneOf' conditional failed, one must be fixed:
['qcom,qcs8300-dsi-ctrl', 'qcom,sa8775p-dsi-ctrl', 'qcom,mdss-dsi-ctrl'] is too long
'qcom,qcs8300-dsi-ctrl' is not one of ['qcom,dsi-ctrl-6g-qcm2290', 'qcom,mdss-dsi-ctrl']
'qcom,mdss-dsi-ctrl' was expected
from schema $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
According to the dsi-controller-main.yaml schema only two strings are allowed one is the SOC specific and other one is generic "qcom,mdss-dsi-ctrl".
Shall I keep only two strings qcom,qcs8300-mdss.yaml and the generic one "qcom,mdss-dsi-ctrl" or if we want to support 3 strings in compatible sting we need to modify the dsi-controller-main.yaml ?
Similarly, I am getting error for dsi_phy compatible string only one SOC specific compatible string is allow.
Thanks,
Ayushi
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes
2025-10-05 16:48 ` Ayushi Makhija
@ 2025-10-05 22:01 ` Dmitry Baryshkov
2025-10-05 23:53 ` Ayushi Makhija
0 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2025-10-05 22:01 UTC (permalink / raw)
To: Ayushi Makhija
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
robdclark, sean, marijn.suijten, andersson, robh, robh+dt,
krzk+dt, konradybcio, conor+dt, andrzej.hajda, neil.armstrong,
rfoss, Laurent.pinchart, jonas, jernej.skrabec, quic_rajeevny,
quic_vproddut, quic_jesszhan
On Sun, 5 Oct 2025 at 19:49, Ayushi Makhija <quic_amakhija@quicinc.com> wrote:
>
> On 9/26/2025 3:32 AM, Dmitry Baryshkov wrote:
> > On Thu, Sep 25, 2025 at 11:06:01AM +0530, Ayushi Makhija wrote:
> >> Add device tree nodes for the DSI0 controller with their corresponding
> >> PHY found on Qualcomm QCS8300 SoC.
> >>
> >> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
> >> ---
> >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 95 ++++++++++++++++++++++++++-
> >> 1 file changed, 94 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> >> index e0e1f63fc45b..834ae0522f2f 100644
> >> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> >> @@ -3,6 +3,7 @@
> >> * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> >> */
> >>
> >> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
> >> #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
> >> #include <dt-bindings/clock/qcom,rpmh.h>
> >> #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
> >> @@ -4854,6 +4855,13 @@ dpu_intf0_out: endpoint {
> >> remote-endpoint = <&mdss_dp0_in>;
> >> };
> >> };
> >> +
> >> + port@1 {
> >> + reg = <1>;
> >> + dpu_intf1_out: endpoint {
> >> + remote-endpoint = <&mdss_dsi0_in>;
> >> + };
> >> + };
> >> };
> >>
> >> mdp_opp_table: opp-table {
> >> @@ -4881,6 +4889,89 @@ opp-650000000 {
> >> };
> >> };
> >>
> >> + mdss_dsi0: dsi@ae94000 {
> >> + compatible = "qcom,sa8775p-dsi-ctrl","qcom,mdss-dsi-ctrl";
> >
> > qcom,qcs8300-dsi-ctrl. You might use three compatibles (qcs8300, sa8775p
> > and the generic one), but there should be qcs8300 one.
> >
>
> Hi Dmitry,
>
> If I am adding three compatible string for ctrl,
>
> compatible = "qcom,qcs8300-dsi-ctrl",
> "qcom,sa8775p-dsi-ctrl",
> "qcom,mdss-dsi-ctrl";
>
> while validating dt-binding and dtsi against dt-schema. I am getting below errors
>
>
> /local/mnt/workspace/amakhija/linux_next/linux/arch/arm64/boot/dts/qcom/qcs8300-ride.dtb: dsi@ae94000: compatible: 'oneOf' conditional failed, one must be fixed:
> ['qcom,qcs8300-dsi-ctrl', 'qcom,sa8775p-dsi-ctrl', 'qcom,mdss-dsi-ctrl'] is too long
> 'qcom,qcs8300-dsi-ctrl' is not one of ['qcom,dsi-ctrl-6g-qcm2290', 'qcom,mdss-dsi-ctrl']
> 'qcom,mdss-dsi-ctrl' was expected
> from schema $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
>
> According to the dsi-controller-main.yaml schema only two strings are allowed one is the SOC specific and other one is generic "qcom,mdss-dsi-ctrl".
>
> Shall I keep only two strings qcom,qcs8300-mdss.yaml and the generic one "qcom,mdss-dsi-ctrl" or if we want to support 3 strings in compatible sting we need to modify the dsi-controller-main.yaml ?
Of course.
> Similarly, I am getting error for dsi_phy compatible string only one SOC specific compatible string is allow.
So, what's the question? You are adding support for the platform. So
yes, you need to modify the schema.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes
2025-10-05 22:01 ` Dmitry Baryshkov
@ 2025-10-05 23:53 ` Ayushi Makhija
0 siblings, 0 replies; 14+ messages in thread
From: Ayushi Makhija @ 2025-10-05 23:53 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
robdclark, sean, marijn.suijten, andersson, robh, robh+dt,
krzk+dt, konradybcio, conor+dt, andrzej.hajda, neil.armstrong,
rfoss, Laurent.pinchart, jonas, jernej.skrabec, quic_rajeevny,
quic_vproddut, quic_jesszhan
On 10/6/2025 3:31 AM, Dmitry Baryshkov wrote:
> On Sun, 5 Oct 2025 at 19:49, Ayushi Makhija <quic_amakhija@quicinc.com> wrote:
>>
>> On 9/26/2025 3:32 AM, Dmitry Baryshkov wrote:
>>> On Thu, Sep 25, 2025 at 11:06:01AM +0530, Ayushi Makhija wrote:
>>>> Add device tree nodes for the DSI0 controller with their corresponding
>>>> PHY found on Qualcomm QCS8300 SoC.
>>>>
>>>> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 95 ++++++++++++++++++++++++++-
>>>> 1 file changed, 94 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>> index e0e1f63fc45b..834ae0522f2f 100644
>>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>> @@ -3,6 +3,7 @@
>>>> * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>>>> */
>>>>
>>>> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
>>>> #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
>>>> #include <dt-bindings/clock/qcom,rpmh.h>
>>>> #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
>>>> @@ -4854,6 +4855,13 @@ dpu_intf0_out: endpoint {
>>>> remote-endpoint = <&mdss_dp0_in>;
>>>> };
>>>> };
>>>> +
>>>> + port@1 {
>>>> + reg = <1>;
>>>> + dpu_intf1_out: endpoint {
>>>> + remote-endpoint = <&mdss_dsi0_in>;
>>>> + };
>>>> + };
>>>> };
>>>>
>>>> mdp_opp_table: opp-table {
>>>> @@ -4881,6 +4889,89 @@ opp-650000000 {
>>>> };
>>>> };
>>>>
>>>> + mdss_dsi0: dsi@ae94000 {
>>>> + compatible = "qcom,sa8775p-dsi-ctrl","qcom,mdss-dsi-ctrl";
>>>
>>> qcom,qcs8300-dsi-ctrl. You might use three compatibles (qcs8300, sa8775p
>>> and the generic one), but there should be qcs8300 one.
>>>
>>
>> Hi Dmitry,
>>
>> If I am adding three compatible string for ctrl,
>>
>> compatible = "qcom,qcs8300-dsi-ctrl",
>> "qcom,sa8775p-dsi-ctrl",
>> "qcom,mdss-dsi-ctrl";
>>
>> while validating dt-binding and dtsi against dt-schema. I am getting below errors
>>
>>
>> /local/mnt/workspace/amakhija/linux_next/linux/arch/arm64/boot/dts/qcom/qcs8300-ride.dtb: dsi@ae94000: compatible: 'oneOf' conditional failed, one must be fixed:
>> ['qcom,qcs8300-dsi-ctrl', 'qcom,sa8775p-dsi-ctrl', 'qcom,mdss-dsi-ctrl'] is too long
>> 'qcom,qcs8300-dsi-ctrl' is not one of ['qcom,dsi-ctrl-6g-qcm2290', 'qcom,mdss-dsi-ctrl']
>> 'qcom,mdss-dsi-ctrl' was expected
>> from schema $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
>>
>> According to the dsi-controller-main.yaml schema only two strings are allowed one is the SOC specific and other one is generic "qcom,mdss-dsi-ctrl".
>>
>> Shall I keep only two strings qcom,qcs8300-mdss.yaml and the generic one "qcom,mdss-dsi-ctrl" or if we want to support 3 strings in compatible sting we need to modify the dsi-controller-main.yaml ?
>
> Of course.
>
>> Similarly, I am getting error for dsi_phy compatible string only one SOC specific compatible string is allow.
>
> So, what's the question? You are adding support for the platform. So
> yes, you need to modify the schema.
>
Thanks Dmitry for the clarification will modify the dsi-controller-main.yaml to support more than 2 strings in the compatible and dsi-phy-7nm.yaml schema to support more than one string in the compatible.
Thanks,
Ayushi
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: qcs8300-ride: add anx7625 DSI to DP bridge node
2025-09-25 5:35 [PATCH 0/3] Add DSI display support for QCS8300 target Ayushi Makhija
2025-09-25 5:36 ` [PATCH 1/3] dt-bindings: display: msm: document DSI controller and phy on QCS8300 Ayushi Makhija
2025-09-25 5:36 ` [PATCH 2/3] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes Ayushi Makhija
@ 2025-09-25 5:36 ` Ayushi Makhija
2025-09-25 22:03 ` Dmitry Baryshkov
2 siblings, 1 reply; 14+ messages in thread
From: Ayushi Makhija @ 2025-09-25 5:36 UTC (permalink / raw)
To: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
Cc: Ayushi Makhija, robdclark, dmitry.baryshkov, sean,
marijn.suijten, andersson, robh, robh+dt, krzk+dt, konradybcio,
conor+dt, andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart,
jonas, jernej.skrabec, quic_rajeevny, quic_vproddut,
quic_jesszhan
Add anx7625 DSI to DP bridge device node.
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 170 ++++++++++++++++++++++
1 file changed, 170 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index 891e49602c97..5d4040376857 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -24,6 +24,64 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ vreg_12p0: vreg-12p0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_12P0";
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vreg_5p0: vreg-5p0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_5P0";
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ vin-supply = <&vreg_12p0>;
+ };
+
+ vreg_1p8: vreg-1p8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_1P8";
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ vin-supply = <&vreg_5p0>;
+ };
+
+ vreg_1p0: vreg-1p0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_1P0";
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+
+ vin-supply = <&vreg_1p8>;
+ };
+
+ vreg_3p0: vreg-3p0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_3P0";
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ vin-supply = <&vreg_12p0>;
+ };
+
dp0-connector {
compatible = "dp-connector";
label = "DP0";
@@ -36,6 +94,18 @@ dp0_connector_in: endpoint {
};
};
+ dp-dsi0-connector {
+ compatible = "dp-connector";
+ label = "DSI0";
+ type = "full-size";
+
+ port {
+ dp_dsi0_connector_in: endpoint {
+ remote-endpoint = <&dsi2dp_bridge_out>;
+ };
+ };
+ };
+
regulator-usb2-vbus {
compatible = "regulator-fixed";
regulator-name = "USB2_VBUS";
@@ -316,6 +386,70 @@ &gpu_zap_shader {
firmware-name = "qcom/qcs8300/a623_zap.mbn";
};
+&i2c8 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ io_expander: gpio@74 {
+ compatible = "ti,tca9539";
+ reg = <0x74>;
+ interrupts-extended = <&tlmm 93 IRQ_TYPE_EDGE_BOTH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reset-gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&io_expander_intr_active>,
+ <&io_expander_reset_active>;
+ pinctrl-names = "default";
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bridge@58 {
+ compatible = "analogix,anx7625";
+ reg = <0x58>;
+ interrupts-extended = <&io_expander 2 IRQ_TYPE_EDGE_FALLING>;
+ enable-gpios = <&io_expander 1 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
+ vdd10-supply = <&vreg_1p0>;
+ vdd18-supply = <&vreg_1p8>;
+ vdd33-supply = <&vreg_3p0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi2dp_bridge_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi2dp_bridge_out: endpoint {
+ remote-endpoint = <&dp_dsi0_connector_in>;
+ };
+ };
+ };
+ };
+ };
+ };
+};
+
&pmm8650au_1_gpios {
usb2_en: usb2-en-state {
pins = "gpio7";
@@ -353,10 +487,31 @@ &mdss_dp0_phy {
status = "okay";
};
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l4a>;
+
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&dsi2dp_bridge_in>;
+};
+
&qupv3_id_0 {
status = "okay";
};
+&qupv3_id_1 {
+ status = "okay";
+};
+
&remoteproc_adsp {
firmware-name = "qcom/qcs8300/adsp.mbn";
status = "okay";
@@ -419,6 +574,21 @@ dp_hot_plug_det: dp-hot-plug-det-state {
function = "edp0_hot";
bias-disable;
};
+
+ io_expander_intr_active: io-expander-intr-active-state {
+ pins = "gpio93";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ io_expander_reset_active: io-expander-reset-active-state {
+ pins = "gpio66";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
};
&uart7 {
--
2.34.1
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: qcs8300-ride: add anx7625 DSI to DP bridge node
2025-09-25 5:36 ` [PATCH 3/3] arm64: dts: qcom: qcs8300-ride: add anx7625 DSI to DP bridge node Ayushi Makhija
@ 2025-09-25 22:03 ` Dmitry Baryshkov
0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 22:03 UTC (permalink / raw)
To: Ayushi Makhija
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
robdclark, sean, marijn.suijten, andersson, robh, robh+dt,
krzk+dt, konradybcio, conor+dt, andrzej.hajda, neil.armstrong,
rfoss, Laurent.pinchart, jonas, jernej.skrabec, quic_rajeevny,
quic_vproddut, quic_jesszhan
On Thu, Sep 25, 2025 at 11:06:02AM +0530, Ayushi Makhija wrote:
> Add anx7625 DSI to DP bridge device node.
>
> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 170 ++++++++++++++++++++++
> 1 file changed, 170 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread