From: Wei Huang <wehuang@redhat.com>
To: Maxim Levitsky <mlevitsk@redhat.com>, kvm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, pbonzini@redhat.com,
vkuznets@redhat.com, seanjc@google.com, joro@8bytes.org,
bp@alien8.de, tglx@linutronix.de, mingo@redhat.com,
x86@kernel.org, jmattson@google.com, wanpengli@tencent.com,
bsd@redhat.com, dgilbert@redhat.com, luto@amacapital.net
Subject: Re: [PATCH v3 3/4] KVM: SVM: Add support for SVM instruction address check change
Date: Tue, 26 Jan 2021 09:39:17 -0600 [thread overview]
Message-ID: <aee0d84b-52b6-bf1e-557f-5990dfe4000d@amd.com> (raw)
In-Reply-To: <f8a2fbc829a553b936b8babc5c1df2b1e88f51d7.camel@redhat.com>
On 1/26/21 5:52 AM, Maxim Levitsky wrote:
> On Tue, 2021-01-26 at 03:18 -0500, Wei Huang wrote:
>> New AMD CPUs have a change that checks #VMEXIT intercept on special SVM
>> instructions before checking their EAX against reserved memory region.
>> This change is indicated by CPUID_0x8000000A_EDX[28]. If it is 1, #VMEXIT
>> is triggered before #GP. KVM doesn't need to intercept and emulate #GP
>> faults as #GP is supposed to be triggered.
>>
>> Co-developed-by: Bandan Das <bsd@redhat.com>
>> Signed-off-by: Bandan Das <bsd@redhat.com>
>> Signed-off-by: Wei Huang <wei.huang2@amd.com>
>> Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
>> ---
>> arch/x86/include/asm/cpufeatures.h | 1 +
>> arch/x86/kvm/svm/svm.c | 3 +++
>> 2 files changed, 4 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index 84b887825f12..ea89d6fdd79a 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -337,6 +337,7 @@
>> #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
>> #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */
>> #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */
>> +#define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */
>>
>> /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
>> #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
>> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
>> index e5ca01e25e89..f9233c79265b 100644
>> --- a/arch/x86/kvm/svm/svm.c
>> +++ b/arch/x86/kvm/svm/svm.c
>> @@ -1036,6 +1036,9 @@ static __init int svm_hardware_setup(void)
>> }
>> }
>>
>> + if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
>> + svm_gp_erratum_intercept = false;
>> +
> Again, I would make svm_gp_erratum_intercept a tri-state module param,
> and here if it is in 'auto' state do this.
>
I will try to craft a param patch and see if it flies...
next prev parent reply other threads:[~2021-01-26 15:45 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-26 8:18 [PATCH v3 0/4] Handle #GP for SVM execution instructions Wei Huang
2021-01-26 8:18 ` [PATCH v3 1/4] KVM: x86: Factor out x86 instruction emulation with decoding Wei Huang
2021-01-26 8:18 ` [PATCH v3 2/4] KVM: SVM: Add emulation support for #GP triggered by SVM instructions Wei Huang
2021-01-26 11:34 ` Paolo Bonzini
2021-01-26 11:50 ` Maxim Levitsky
2021-01-26 8:18 ` [PATCH v3 3/4] KVM: SVM: Add support for SVM instruction address check change Wei Huang
2021-01-26 11:52 ` Maxim Levitsky
2021-01-26 15:39 ` Wei Huang [this message]
2021-01-26 8:18 ` [PATCH v3 4/4] KVM: SVM: Support #GP handling for the case of nested on nested Wei Huang
2021-01-26 11:39 ` Paolo Bonzini
2021-01-26 11:59 ` Maxim Levitsky
2021-01-26 11:39 ` [PATCH v3 0/4] Handle #GP for SVM execution instructions Paolo Bonzini
2021-01-26 15:05 ` Wei Huang
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