Re: [net-next,PATCH v2] enetc: Increase eMDIO MDC rate to 2.5 MHz

[Marek Vasut <marex@nabladev.com>]

On 9/30/26 5:40 AM, Wei Fang wrote:
> Sorry, this email was missed because it did not match the filtering rules I set.

No worries.

> Hi Valdimir and Claudiu,
> 
> Please take a look at this patch, it may affect LS1028A and S32N7 platforms.
> 
>> The current eMDIO MDC rate is 558 kHz on i.MX95 B0. This is very low,
> 
> The system clock of i.MX95 NETC is 333MHz, AFAIU, the MDC rate should be
> 333/(2*258+1) = 644KHz. I'm confused that why you said the rate is 558KHz.

That is what I observe on a scope on local MX95 board (not the EVK).

>> but also very compatible. However, for example NXP TJA1120 PHY needs
>> at minimum 1 MHz MDC clock and 558 kHz does not work with that PHY.
> 
> We previously used the TJA1120-SDBR daughter card to connect to the ENETC
> interface (RGMII) of the i.MX95 19x19 EVK board. However, we did not encounter
> any issues with MDIO access.

Most PHYs are fine with the low frequency.

> Furthermore, I did not see a minimum MDC
> frequency rate of 1MHz on the TJA1120 datasheet. I'm not sure if this is an errata
> of TJA1120.

The TJA1120 RM is not public, but look at its predecessor:

https://www.nxp.com/docs/en/data-sheet/TJA1101B.pdf

Page 46 bottom
Table 37. Dynamic characteristics...continued
Tclk(MDC) MDC ... clock period ... Min 400 ns

400ns ~= 2.5 MHz .

>> As a minimum change, increase the MDC clock to 2.5 MHz which matches
> 
> The prerequisite is that NETC system clock is 333MHz, so that you can get a
> MDC clock rate of 2.5MHz (333/(2*66 + 1)). But unfortunately, not all NETC
> versions have a 333MHz system clock. For example, LS1028A is 400MHz, so
> the MDC rate will be 3MHz, which will be a problem.
Yes, this is my concern.

Are those clock which feed MDC clock available via clock framework on LS 
? If so, we could calculate the divider based on those clock.