Re: [net-next,PATCH v2] enetc: Increase eMDIO MDC rate to 2.5 MHz

[Marek Vasut <marex@nabladev.com>]

On 9/30/26 8:12 AM, Wei Fang wrote:
>>>> The current eMDIO MDC rate is 558 kHz on i.MX95 B0. This is very low,
>>>
>>> The system clock of i.MX95 NETC is 333MHz, AFAIU, the MDC rate should
>>> be
>>> 333/(2*258+1) = 644KHz. I'm confused that why you said the rate is 558KHz.
>>
>> That is what I observe on a scope on local MX95 board (not the EVK).
> 
> Clark helped measure the MDC rate on the 95 EVK board this morning, and the
> result was 644KHz, which is consistent with the theoretical value. The scope's
> accuracy or other factors may be causing you to observe a rate of 558kHz.

That 644 kHz and 558 kHz differs too much to be an equipment 
miscalibration / misuse.

> But
> anyway, the description of 558kHz is indeed confusing because it does not match
> the theoretical value.

Do you know from which clock are the MDC clock derived from on MX95 ?

>>>> but also very compatible. However, for example NXP TJA1120 PHY needs
>>>> at minimum 1 MHz MDC clock and 558 kHz does not work with that PHY.
>>>
>>> We previously used the TJA1120-SDBR daughter card to connect to the
>>> ENETC interface (RGMII) of the i.MX95 19x19 EVK board. However, we did
>>> not encounter any issues with MDIO access.
>>
>> Most PHYs are fine with the low frequency.
> 
> Yes, but the example you gave is TJA1120, and we also connected to TJA1120
> without this problem, so this is what puzzles me.

[...]

>> Page 46 bottom
>> Table 37. Dynamic characteristics...continued
>> Tclk(MDC) MDC ... clock period ... Min 400 ns
>>
>> 400ns ~= 2.5 MHz .
> 
> Thanks, I find the similar context in TJA1120's datasheet. The max period is
> 1000ns, so the min rate is 1MHz. It's weird that we did not see any MDIO
> access issues with TJA1120. I saw a note about MDC timing: "Not measured
> in production, guaranteed by design." It's possible that the minimum of 1MHz
> is a theoretical value, and it may actually work even below 1MHz.

I got a report it is problematic, hence this patch. But maybe this is 
also related to the 558 kHz MDC clock I measure locally vs. 644 kHz MDC 
clock on your end.

>>>> As a minimum change, increase the MDC clock to 2.5 MHz which matches
>>>
>>> The prerequisite is that NETC system clock is 333MHz, so that you can
>>> get a MDC clock rate of 2.5MHz (333/(2*66 + 1)). But unfortunately,
>>> not all NETC versions have a 333MHz system clock. For example, LS1028A
>>> is 400MHz, so the MDC rate will be 3MHz, which will be a problem.
>> Yes, this is my concern.
>>
>> Are those clock which feed MDC clock available via clock framework on LS ? If
>> so, we could calculate the divider based on those clock.
> 
> No, we typically hardcode the clock frequency in the driver based on the NETC
> version. Another simple method is to set the divisor to 166 instead of 66, which
> will not cause any problems for using a 400MHz NETC.

Hmmmm, are those clock available on MX95 ? Maybe we can do some sort of 
fallback -- assume 166 MHz clock on LS, and obtain the clock and clock 
rate via clock framework on MX95 ?