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From: Wei Fang <wei.fang@nxp.com>
To: Marek Vasut <marex@nabladev.com>,
	Clark Wang <xiaoning.wang@nxp.com>,
	Claudiu Manoil <claudiu.manoil@nxp.com>,
	Vladimir Oltean <vladimir.oltean@nxp.com>
Cc: "David S. Miller" <davem@davemloft.net>,
	Andrew Lunn <andrew+netdev@lunn.ch>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	"imx@lists.linux.dev" <imx@lists.linux.dev>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>
Subject: RE: [net-next,PATCH v2] enetc: Increase eMDIO MDC rate to 2.5 MHz
Date: Wed, 30 Sep 2026 03:40:56 +0000	[thread overview]
Message-ID: <AS4PR04MB93382AF6B2AC7B5F421019BB888B2@AS4PR04MB9338.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <20260924180607.60932-1-marex@nabladev.com>

Sorry, this email was missed because it did not match the filtering rules I set.

Hi Valdimir and Claudiu,

Please take a look at this patch, it may affect LS1028A and S32N7 platforms.

> The current eMDIO MDC rate is 558 kHz on i.MX95 B0. This is very low,

The system clock of i.MX95 NETC is 333MHz, AFAIU, the MDC rate should be
333/(2*258+1) = 644KHz. I'm confused that why you said the rate is 558KHz.

> but also very compatible. However, for example NXP TJA1120 PHY needs
> at minimum 1 MHz MDC clock and 558 kHz does not work with that PHY.

We previously used the TJA1120-SDBR daughter card to connect to the ENETC
interface (RGMII) of the i.MX95 19x19 EVK board. However, we did not encounter
any issues with MDIO access. Furthermore, I did not see a minimum MDC
frequency rate of 1MHz on the TJA1120 datasheet. I'm not sure if this is an errata
of TJA1120.

> 
> As a minimum change, increase the MDC clock to 2.5 MHz which matches

The prerequisite is that NETC system clock is 333MHz, so that you can get a
MDC clock rate of 2.5MHz (333/(2*66 + 1)). But unfortunately, not all NETC
versions have a 333MHz system clock. For example, LS1028A is 400MHz, so
the MDC rate will be 3MHz, which will be a problem.

> the 802.3 specification. Also, even old PHYs like LAN8210Ai, KSZ8794,
> DP83822 support up to 2.5 MHz MDC clock frequency, and it covers the
> NXP TJA1120 as well. There is no known rationale for why the 558 kHz
> was picked when the eMDIO driver was added.
> 

> Signed-off-by: Marek Vasut <marex@nabladev.com>
> ---
> Cc: "David S. Miller" <davem@davemloft.net>
> Cc: Andrew Lunn <andrew+netdev@lunn.ch>
> Cc: Clark Wang <xiaoning.wang@nxp.com>
> Cc: Claudiu Manoil <claudiu.manoil@nxp.com>
> Cc: Eric Dumazet <edumazet@google.com>
> Cc: Jakub Kicinski <kuba@kernel.org>
> Cc: Paolo Abeni <pabeni@redhat.com>
> Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
> Cc: Wei Fang <wei.fang@nxp.com>
> Cc: imx@lists.linux.dev
> Cc: linux-kernel@vger.kernel.org
> Cc: netdev@vger.kernel.org
> ---
> V2: Use 2.5 MHz per 802.3 spec, update commit message
> ---
>  drivers/net/ethernet/freescale/enetc/enetc_mdio.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
> b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
> index 998aaa394e9c4..a90a04a47befd 100644
> --- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
> +++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
> @@ -24,7 +24,7 @@
> 
>  #define ENETC_EMDIO_CFG \
>  	(MDIO_CFG_HOLD(2) | \
> -	 MDIO_CFG_CLKDIV(258) | \
> +	 MDIO_CFG_CLKDIV(66) | \
>  	 MDIO_CFG_NEG)
> 
>  #define MDIO_CTL_DEV_ADDR(x)	((x) & 0x1f)
> --
> 2.53.0


  parent reply	other threads:[~2026-09-30  3:41 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-24 18:05 Marek Vasut
2026-09-25 18:43 ` netdev-bot+sashiko
2026-09-30  2:10 ` patchwork-bot+netdevbpf
2026-09-30  2:21   ` Marek Vasut
2026-09-30 20:51     ` Jakub Kicinski
2026-09-30  3:40 ` Wei Fang [this message]
2026-09-30  4:19   ` Marek Vasut
2026-09-30  6:12     ` Wei Fang
2026-09-30 13:11       ` Andrew Lunn
2026-10-01  0:04         ` Wei Fang
2026-09-30 13:27       ` Marek Vasut
2026-10-01  0:45         ` Wei Fang
2026-10-01  1:34           ` Marek Vasut
2026-10-01 10:57             ` Wei Fang
2026-10-01 13:53               ` Andrew Lunn
2026-10-01 22:43                 ` Marek Vasut
2026-10-08  3:08                   ` Wei Fang
2026-10-01 22:51             ` Jakub Kicinski
2026-10-01 23:11               ` Marek Vasut
2026-10-01 22:00         ` Marek Vasut
2026-10-08  2:34           ` Wei Fang
2026-10-12 17:05             ` Marek Vasut
2026-10-13  2:17               ` Wei Fang
2026-10-15 21:20                 ` Marek Vasut
2026-10-13 15:25     ` Vladimir Oltean
2026-10-16 19:09       ` Marek Vasut

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