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From: Frank Li <Frank.li@nxp.com>
To: Koichiro Den <den@valinux.co.jp>
Cc: Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>,
	Manivannan Sadhasivam <mani@kernel.org>,
	Marek Vasut <marek.vasut+renesas@mailbox.org>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 09/12] dmaengine: dw-edma-pcie: Add register offset match flag
Date: Thu, 21 May 2026 12:17:21 -0400	[thread overview]
Message-ID: <ag8wETTj4HhAxGYX@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20260521063115.2842238-10-den@valinux.co.jp>

On Thu, May 21, 2026 at 03:31:12PM +0900, Koichiro Den wrote:
> Add a match-data flag for devices whose DMA register block starts at an
> offset inside the mapped BAR. Existing Synopsys EDDA and AMD/Xilinx MDB
> matches keep using the BAR mapping base directly.
>
> No functional change intended.
>
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
> ---
>  drivers/dma/dw-edma/dw-edma-pcie.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
> index 651269708cc5..6b375a58c550 100644
> --- a/drivers/dma/dw-edma/dw-edma-pcie.c
> +++ b/drivers/dma/dw-edma/dw-edma-pcie.c
> @@ -88,6 +88,7 @@ struct dw_edma_pcie_match_data {
>
>  #define DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF	BIT(0)
>  #define DW_EDMA_PCIE_F_RAW_SLAVE_ADDR	BIT(1)
> +#define DW_EDMA_PCIE_F_REG_OFFSET	BIT(2)
>
>  static const struct dw_edma_pcie_data snps_edda_data = {
>  	/* eDMA registers location */
> @@ -450,6 +451,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
>  	chip->reg_base = pcim_iomap_table(pdev)[dma_data->rg.bar];
>  	if (!chip->reg_base)
>  		return -ENOMEM;
> +	if (match->flags & DW_EDMA_PCIE_F_REG_OFFSET)
> +		chip->reg_base += dma_data->rg.off;

suppose default rg.off is 0, so needn't flag DW_EDMA_PCIE_F_REG_OFFSET.

Frank

>
>  	for (i = 0; i < chip->ll_wr_cnt && !non_ll; i++) {
>  		struct dw_edma_region *ll_region = &chip->ll_region_wr[i];
> --
> 2.51.0
>

  reply	other threads:[~2026-05-21 16:17 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-21  6:31 [PATCH 00/12] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3) Koichiro Den
2026-05-21  6:31 ` [PATCH 01/12] dmaengine: Make dma_get_slave_channel() public Koichiro Den
2026-05-21  6:31 ` [PATCH 02/12] dmaengine: dw-edma: Add channel lookup helper Koichiro Den
2026-05-21 15:50   ` Frank Li
2026-05-21  6:31 ` [PATCH 03/12] dmaengine: dw-edma: Add per-channel interrupt routing control Koichiro Den
2026-05-21  6:31 ` [PATCH 04/12] dmaengine: dw-edma: Add partial channel ownership mode Koichiro Den
2026-05-21  6:31 ` [PATCH 05/12] dmaengine: dw-edma-pcie: Add capability match data Koichiro Den
2026-05-21 16:06   ` Frank Li
2026-05-22 14:38     ` Koichiro Den
2026-05-22 20:54       ` Frank Li
2026-05-21  6:31 ` [PATCH 06/12] dmaengine: dw-edma-pcie: Rename DMA data copy Koichiro Den
2026-05-21 16:10   ` Frank Li
2026-05-22 14:41     ` Koichiro Den
2026-05-21  6:31 ` [PATCH 07/12] dmaengine: dw-edma-pcie: Add default IRQ match data Koichiro Den
2026-05-21 16:12   ` Frank Li
2026-05-21  6:31 ` [PATCH 08/12] dmaengine: dw-edma-pcie: Add raw slave address match flag Koichiro Den
2026-05-21 16:15   ` Frank Li
2026-05-22 14:45     ` Koichiro Den
2026-05-21  6:31 ` [PATCH 09/12] dmaengine: dw-edma-pcie: Add register offset " Koichiro Den
2026-05-21 16:17   ` Frank Li [this message]
2026-05-22 14:57     ` Koichiro Den
2026-05-22 20:51       ` Frank Li
2026-05-21  6:31 ` [PATCH 10/12] dmaengine: dw-edma-pcie: Factor descriptor block addresses Koichiro Den
2026-05-21 16:21   ` Frank Li
2026-05-21  6:31 ` [PATCH 11/12] dmaengine: dw-edma-pcie: Handle optional data blocks Koichiro Den
2026-05-21 16:25   ` Frank Li
2026-05-21  6:31 ` [PATCH 12/12] dmaengine: dw-edma-pcie: Add chip flags match data Koichiro Den
2026-05-21 16:26   ` Frank Li

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