Re: [PATCH v2 2/3] x86/apic: Introduce a variable to track the number of EILVT registers

Re: [PATCH v2 2/3] x86/apic: Introduce a variable to track the number of EILVT registers

[Christian Ludloff]

> + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC))
> + apic_eilvt_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT));

BKDG #21656, #21922, and #24141 for K7 were not published.
If you find them internally at AMD, consider publishing them.  :)
That way they could be archived, and referenced from then on.

BKDG #26094 for K8 Fam Fh DDR1 documents 4 extended LVTs.
BKDG #32559 for K8 Fam Fh DDR2 documents 1 extended LVT.
BKDG #41256 for K8 Fam 11h (LG) documents 4 extended LVTs.

Fam 10h/12h, 14h and 16h, and 15h all have 4 – no surprises.

The Fam 10h BKDG (#31116) has an explicit entry in its "Major
Changes Relative to Family 0Fh Processors" section: "Number
of extended LVT interrupts in APIC increased to 4." – AMD may
want to clarify what was correct vs not for those old K8 models.

> + if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> + apic_eilvt_count = APIC_EILVT_NR_AMD_10H;

This seems... unsafe?

--
C.

Re: [PATCH v2 2/3] x86/apic: Introduce a variable to track the number of EILVT registers

[Christian Ludloff]

On Fri, May 15, 2026 at 4:48 AM Christian Ludloff <ludloff@gmail.com> wrote:
>
> > + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC))
> > + apic_eilvt_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT));
>
> BKDG #21656, #21922, and #24141 for K7 were not published.
> If you find them internally at AMD, consider publishing them.  :)
> That way they could be archived, and referenced from then on.

minor extra K7 quirk, documented in the K7 datasheet (#21016):

before model 2, the chip was missing two of the pins required for
proper APIC operation – so the APIC didn't quite work back then

> BKDG #26094 for K8 Fam Fh DDR1 documents 4 extended LVTs.

I mis-read that one – correction – it's 0 there, not 4

also, supposedly no bit 31 = 1 in the version register, but does have
registers 400h and 410h (but not the other/later extended registers)

> BKDG #32559 for K8 Fam Fh DDR2 documents 1 extended LVT.
> BKDG #41256 for K8 Fam 11h (LG) documents 4 extended LVTs.
>
> Fam 10h/12h, 14h and 16h, and 15h all have 4 – no surprises.
>
> The Fam 10h BKDG (#31116) has an explicit entry in its "Major
> Changes Relative to Family 0Fh Processors" section: "Number
> of extended LVT interrupts in APIC increased to 4." – AMD may
> want to clarify what was correct vs not for those old K8 models.

per the correction above – K8 went from 0 to 1 to 4 extended LVTs

> > + if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> > + apic_eilvt_count = APIC_EILVT_NR_AMD_10H;
>
> This seems... unsafe?

double-check it w.r.t. K7 and K8 Fam Fh DDR1, please

--
C.

Re: [PATCH v2 2/3] x86/apic: Introduce a variable to track the number of EILVT registers

[Naveen N Rao]

On Fri, May 15, 2026 at 06:30:07AM -0700, Christian Ludloff wrote:
> On Fri, May 15, 2026 at 4:48 AM Christian Ludloff <ludloff@gmail.com> wrote:
> >
> > > + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC))
> > > + apic_eilvt_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT));
> >
> > BKDG #21656, #21922, and #24141 for K7 were not published.
> > If you find them internally at AMD, consider publishing them.  :)
> > That way they could be archived, and referenced from then on.
> 
> minor extra K7 quirk, documented in the K7 datasheet (#21016):
> 
> before model 2, the chip was missing two of the pins required for
> proper APIC operation – so the APIC didn't quite work back then
> 
> > BKDG #26094 for K8 Fam Fh DDR1 documents 4 extended LVTs.
> 
> I mis-read that one – correction – it's 0 there, not 4
> 
> also, supposedly no bit 31 = 1 in the version register, but does have
> registers 400h and 410h (but not the other/later extended registers)
> 
> > BKDG #32559 for K8 Fam Fh DDR2 documents 1 extended LVT.
> > BKDG #41256 for K8 Fam 11h (LG) documents 4 extended LVTs.
> >
> > Fam 10h/12h, 14h and 16h, and 15h all have 4 – no surprises.
> >
> > The Fam 10h BKDG (#31116) has an explicit entry in its "Major
> > Changes Relative to Family 0Fh Processors" section: "Number
> > of extended LVT interrupts in APIC increased to 4." – AMD may
> > want to clarify what was correct vs not for those old K8 models.
> 
> per the correction above – K8 went from 0 to 1 to 4 extended LVTs

Right, I looked up what I could. The fallback below is explicitly for 
addressing those.

> 
> > > + if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> > > + apic_eilvt_count = APIC_EILVT_NR_AMD_10H;
> >
> > This seems... unsafe?
> 
> double-check it w.r.t. K7 and K8 Fam Fh DDR1, please

This fallback exists purely to retain the current default (except that 
it is now restricted to AMD processors)

The default being 4 (rather than 1 or even 0) is not really an issue 
because this function won't be invoked for older processors.  The common 
case is for this to be invoked with a BIOS-provided offset.  The only 
exception is for IBS for family 0x10, but that family has 4 extended 
LVTs present (see ibs_eilvt_setup()).


- Naveen

[PATCH v2 0/3] Support additional AMD EILVT registers

[Naveen N Rao (AMD)]

This is v2 of the series posted at:
http://lore.kernel.org/r/cover.1775019269.git.naveen@kernel.org

Changes since v1:
- Drop the first two patches that were merged
- Call init_eilvt() from apic_bsp_setup(), rather than 
  setup_local_APIC() so as not to call an __init function from a 
  non-init function. (Kernel 0-day bot)
- Initialize eilvt count to APIC_EILVT_NR_AMD_10H and allocate 
  eilvt_offsets array only on AMD processors.
 
Manali,
I am retaining your Tested-by: tag since the changes are minimal, but 
please reply here if you have concerns with the changes.

--
Future AMD processors will be increasing the number of APIC EILVT 
registers (*). This series adds support for the same along with some 
related cleanups.

(*) https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)


- Naveen


Naveen N Rao (AMD) (3):
  perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10
  x86/apic: Introduce a variable to track the number of EILVT registers
  x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count

 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  2 +-
 arch/x86/events/amd/ibs.c      |  4 ++--
 arch/x86/kernel/apic/apic.c    | 19 +++++++++++++++++--
 4 files changed, 22 insertions(+), 5 deletions(-)


base-commit: 70e7aca9f7ff4d1bee94c5b04973c3dbca1dba00
-- 
2.54.0

[PATCH v2 2/3] x86/apic: Introduce a variable to track the number of EILVT registers

[Naveen N Rao (AMD)]

Future AMD processors will be increasing the number of EILVT registers.
Rather than hardcoding the maximum EILVT register count and using that
everywhere, introduce a variable to track the EILVT register count.

The number of EILVT registers is exposed through the extended APIC
Feature Register (APIC_EFEAT) bits 23:16. Use this to initialize the
count and fall back to the current default (APIC_EILVT_NR_AMD_10H) if
the count is not available.

Export the new variable for KVM since it needs this for supporting
extended APIC register space on AMD.

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
http://lore.kernel.org/r/20260204074452.55453-3-manali.shukla@amd.com as 
a related series adding support for KVM and needing access to the EILVT 
register count.

- Naveen


 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  1 +
 arch/x86/kernel/apic/apic.c    | 12 ++++++++++++
 3 files changed, 15 insertions(+)

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 9cd493d467d4..8b03c7a14706 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -74,6 +74,8 @@ enum apic_intr_mode_id {
 	APIC_SYMMETRIC_IO_NO_ROUTING
 };
 
+extern unsigned int apic_eilvt_count;
+
 /*
  * With 82489DX we can't rely on apic feature bit
  * retrieved via cpuid but still have to deal with
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index bc125c4429dc..ba7657e75ad1 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -134,6 +134,7 @@
 #define		APIC_TDR_DIV_64		0x9
 #define		APIC_TDR_DIV_128	0xA
 #define	APIC_EFEAT	0x400
+#define		APIC_EFEAT_XLC(x)	(((x) >> 16) & 0xff)
 #define	APIC_ECTRL	0x410
 #define APIC_SEOI	0x420
 #define APIC_IER	0x480
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 8c614750a19b..ecbf15399399 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -342,6 +342,8 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
  */
 
 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
+unsigned int apic_eilvt_count __ro_after_init;
+EXPORT_SYMBOL_FOR_KVM(apic_eilvt_count);
 
 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
 {
@@ -410,6 +412,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
 }
 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
 
+static __init void init_eilvt(void)
+{
+	if (cpu_feature_enabled(X86_FEATURE_EXTAPIC))
+		apic_eilvt_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT));
+
+	if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+		apic_eilvt_count = APIC_EILVT_NR_AMD_10H;
+}
+
 /*
  * Program the next event, relative to now
  */
@@ -2344,6 +2355,7 @@ static void __init apic_bsp_setup(bool upmode)
 	if (upmode)
 		apic_bsp_up_setup();
 	setup_local_APIC();
+	init_eilvt();
 
 	enable_IO_APIC();
 	end_local_APIC_setup();
-- 
2.54.0