From: Drew Fustini <fustini@kernel.org>
To: Reinette Chatre <reinette.chatre@intel.com>
Cc: Ben Horgan <ben.horgan@arm.com>, Tony Luck <tony.luck@intel.com>,
James Morse <james.morse@arm.com>,
Dave Martin <Dave.Martin@arm.com>,
Babu Moger <babu.moger@amd.com>, Fenghua Yu <fenghuay@nvidia.com>,
Chen Yu <yu.c.chen@intel.com>, Borislav Petkov <bp@alien8.de>,
Thomas Gleixner <tglx@linutronix.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
Peter Newman <peternewman@google.com>,
"x86@kernel.org" <x86@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [RFC] mpam,x86,fs/resctrl: Generic schema description Proof of Concept
Date: Fri, 5 Jun 2026 22:23:46 -0700 [thread overview]
Message-ID: <aiOu4pJmUmFiyxlu@thelio> (raw)
In-Reply-To: <aiOrznnZjTGywMna@thelio>
On Fri, Jun 05, 2026 at 10:10:38PM -0700, Drew Fustini wrote:
> On Fri, Jun 05, 2026 at 12:35:51PM -0700, Drew Fustini wrote:
> > > As I mentioned in response to Ben [2] there seems to be a mismatch between
> > > architecture requirements here. resctrl uses the value returned by
> > > resctrl_get_default_ctrlval() as the control value that means "no throttling".
> > > For Intel this means min == max but this does not seem to be the case for MPAM
> > > and CBQRI. I am not familiar enough with either to have an alternative proposal here
> > > so I need to become familiar now. There is a bit of backlog on other resctl
> > > work right now so this will take me some time to sort out.
> >
> > Thanks for pointing this out. In that case, it doesn't seem to match
> > what I was thinking of for MB_MIN. The CBQRI reserved bandwidth blocks
> > Rbwb) control can be thought of as a minimum amount of guranteed
> > bandwidth for a control group. Each RCID (e.g. CLOSID) must be assigned
> > at least 1 bandwidth block per the spec. Therefore, the membw.min_bw
> > would need to be 1.
> >
> > There is also a max bandwidth reservation across all control groups
> > (RCIDs / CLOSIDs) so that there will be some amount of unreserved
> > bandwidth. Mweight (1-255) controls how much of that unreserved
> > bandwidth pool that a group can use. Mweight of 0 means no shared
> > bandwidth. I think the membw.min_bw would need to 255 so that all groups
> > get equal share of the unreserved pool.
>
> Sorry, I wasn't thinking about this right. If Mweight is used for MB,
> then membw.max_bw would be 100 (MAX_MBA_BW) and membw.min_bw would be 0
> which means no shared bandwidth.
>
> > It seems like that would be incorrect use of membw.min_bw in both cases?
>
> The issue is really just for Rbwb (reserved bandwidth) as that needs to
> default to the minimum of 1. What about introducing membw.reset_val
> which would be returned by resctrl_get_default_ctrl()?
>
> MB could set membw.reset_val to be the same value as membw.max_bw.
>
> > > > There is no equivalent to MB (percentage throttle) in RISC-V so I would
> > > > want it to be valid to have MB_MIN (minimum reservation) without MB.
> > > >
> > > > I rebased my RISC-V CBQRI v6 series on top of this proof of concept and
> > > > was able to validate it works okay in Qemu:
> > > >
> > > > MB_WGHT:72=255
> > > > MB_MIN:72=756
> > > > L2:64=fff;65=fff
> > > > L3:75=ffff
> > >
> > > Ideally any new support should not break existing user space and the existing
> > > user interface expects a MB entry in the schemata file when the MB resource exists.
> > > Is it possible to emulate the percentage based MB control with MB_WGHT or MB_MIN?
> > > This sounds similar as what is/was planned for MPAM [2].
> >
> > Yes, I think that Mweight could be mapped to the MB concept of
> > throttling. All groups could start with the max Mweight of 255 which
> > could can be represented as 100%.
> >
> > However, I'm not sure what to do about membw.min_bw. Mweight = 0 means
> > it can not use any of the shared unreserved bandwidth pool. If
> > resctrl_get_default_ctrlval() is designed to mean "no throttling", then
> > it seems like the membw.min_bw would need to be 255. But that feels
> > weird for the min_bw value to be equal to the max weight for unreserved
> > bandwidth.
>
> MB would have the typical membw.min_bw = 100, and
> resctrl_get_default_ctrl() would return 100. The controller would be
> programmed with Mweight 255 for 100%.
Sorry - I meant MB would have membw.max_bw = 100 which would cause CBQRI
bandwidth controller to be programmed with Mweight = 255.
Drew
next prev parent reply other threads:[~2026-06-06 5:23 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-29 18:06 Reinette Chatre
2026-06-02 20:23 ` Babu Moger
2026-06-02 22:56 ` Reinette Chatre
2026-06-03 1:14 ` Moger, Babu
2026-06-03 3:55 ` Reinette Chatre
2026-06-03 14:40 ` Babu Moger
2026-06-02 23:32 ` Chen, Yu C
2026-06-03 3:45 ` Reinette Chatre
2026-06-03 11:53 ` Chen, Yu C
2026-06-04 16:37 ` Reinette Chatre
2026-06-05 15:43 ` Chen, Yu C
2026-06-05 16:20 ` Reinette Chatre
2026-06-03 15:15 ` Ben Horgan
2026-06-03 19:34 ` Drew Fustini
2026-06-04 11:24 ` Ben Horgan
2026-06-04 17:38 ` Drew Fustini
2026-06-12 1:30 ` Shaopeng Tan (Fujitsu)
2026-06-17 15:29 ` Reinette Chatre
2026-06-19 1:42 ` Shaopeng Tan (Fujitsu)
2026-06-22 16:10 ` Reinette Chatre
2026-06-23 5:04 ` Shaopeng Tan (Fujitsu)
2026-06-04 21:05 ` Reinette Chatre
2026-06-05 19:35 ` Drew Fustini
2026-06-06 5:10 ` Drew Fustini
2026-06-06 5:23 ` Drew Fustini [this message]
2026-06-04 17:43 ` Reinette Chatre
2026-06-05 14:53 ` Ben Horgan
2026-06-05 15:39 ` Reinette Chatre
2026-06-05 16:37 ` Ben Horgan
2026-06-08 16:16 ` Reinette Chatre
2026-06-09 10:10 ` Ben Horgan
2026-06-09 15:28 ` Reinette Chatre
2026-06-09 16:37 ` Ben Horgan
2026-06-09 17:41 ` Reinette Chatre
2026-06-10 7:09 ` Chen, Yu C
2026-06-10 14:27 ` Chen, Yu C
2026-06-10 16:13 ` Reinette Chatre
2026-06-10 17:57 ` Chen, Yu C
2026-06-10 18:10 ` Reinette Chatre
2026-06-10 15:59 ` Reinette Chatre
2026-06-10 18:05 ` Chen, Yu C
2026-06-11 3:26 ` Chen, Yu C
2026-06-11 15:45 ` Reinette Chatre
2026-06-26 15:46 ` Chen, Yu C
2026-07-02 14:27 ` Ben Horgan
2026-07-03 9:01 ` Chen, Yu C
2026-07-14 21:37 ` Reinette Chatre
2026-07-15 2:49 ` Chen, Yu C
2026-06-10 4:31 ` Drew Fustini
2026-06-10 15:14 ` Reinette Chatre
2026-06-03 18:46 ` Luck, Tony
2026-06-04 10:02 ` Ben Horgan
2026-06-04 21:42 ` Reinette Chatre
2026-07-08 12:56 ` Chen, Yu C
2026-07-14 21:39 ` Reinette Chatre
2026-06-03 22:14 ` Drew Fustini
2026-06-04 21:47 ` Reinette Chatre
2026-06-05 19:48 ` Drew Fustini
2026-06-15 21:05 ` Moger, Babu
2026-06-17 17:18 ` Reinette Chatre
2026-06-17 20:29 ` Babu Moger
2026-06-24 19:08 ` Fenghua Yu
2026-06-24 22:22 ` Reinette Chatre
2026-06-25 1:26 ` Fenghua Yu
2026-06-25 15:43 ` Reinette Chatre
2026-07-10 20:59 ` Fenghua Yu
2026-07-14 22:06 ` Reinette Chatre
2026-07-15 8:34 ` Ben Horgan
2026-07-15 15:41 ` Reinette Chatre
2026-07-16 14:59 ` Ben Horgan
2026-07-16 16:02 ` Luck, Tony
2026-07-16 16:22 ` Ben Horgan
2026-07-16 17:50 ` Reinette Chatre
2026-07-17 10:27 ` Ben Horgan
2026-07-16 16:04 ` Reinette Chatre
2026-07-16 16:44 ` Ben Horgan
2026-07-16 17:07 ` Reinette Chatre
2026-07-17 12:20 ` Ben Horgan
2026-07-17 16:00 ` Reinette Chatre
2026-07-17 16:02 ` Chen, Yu C
2026-07-17 16:55 ` Reinette Chatre
2026-07-02 13:37 ` Ben Horgan
2026-07-02 15:16 ` Fenghua Yu
2026-07-03 13:42 ` Ben Horgan
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