* [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
@ 2017-10-20 0:08 Gayatri Kammela
2017-10-20 6:37 ` Thomas Gleixner
0 siblings, 1 reply; 7+ messages in thread
From: Gayatri Kammela @ 2017-10-20 0:08 UTC (permalink / raw)
To: linux-kernel
Cc: x86, bp, hpa, Gayatri Kammela, Ravi Shankar, Fenghua Yu,
Ricardo Neri, Yang Zhong
Add a few new AVX512 instruction groups/features for enumeration in
/proc/cpuinfo: AVX512_VBMI2, GFNI, VAES, VPCLMULQDQ, AVX512_VNNI,
AVX512_BITALG.
Clear the flags in fpu_xstate_clear_all_cpu_caps().
CPUID.(EAX=7,ECX=0):ECX[bit 6] AVX512_VBMI2
CPUID.(EAX=7,ECX=0):ECX[bit 8] GFNI
CPUID.(EAX=7,ECX=0):ECX[bit 9] VAES
CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512_VNNI
CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
Detailed information of cpuid bits for these features can be found in
the Intel Architecture Instruction Set Extensions and Future Features
Programming Interface document (refer to Table 1-1. and Table 1-2.).
A copy of this document is available at
https://bugzilla.kernel.org/show_bug.cgi?id=197239
Cc: Ravi Shankar <ravi.v.shankar@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Ricardo Neri <ricardo.neri@intel.com>
Cc: Yang Zhong <yang.zhong@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
arch/x86/include/asm/cpufeatures.h | 6 ++++++
arch/x86/kernel/fpu/xstate.c | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 2519c6c801c9..d114279e4c7e 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -294,6 +294,12 @@
#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
+#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
+#define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */
+#define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */
+#define X86_FEATURE_VPCLMULQDQ (16*32+ 10) /* Carry-Less Multiplication Quadword */
+#define X86_FEATURE_AVX512_VNNI (16*32+ 11) /* Vector Neural Network Instructions */
+#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB */
#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index c24ac1efb12d..b899504c7962 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -76,6 +76,12 @@ void fpu__xstate_clear_all_cpu_caps(void)
setup_clear_cpu_cap(X86_FEATURE_XGETBV1);
setup_clear_cpu_cap(X86_FEATURE_AVX512VBMI);
setup_clear_cpu_cap(X86_FEATURE_PKU);
+ setup_clear_cpu_cap(X86_FEATURE_AVX512_VBMI2);
+ setup_clear_cpu_cap(X86_FEATURE_GFNI);
+ setup_clear_cpu_cap(X86_FEATURE_VAES);
+ setup_clear_cpu_cap(X86_FEATURE_VPCLMULQDQ);
+ setup_clear_cpu_cap(X86_FEATURE_AVX512_VNNI);
+ setup_clear_cpu_cap(X86_FEATURE_AVX512_BITALG);
setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW);
setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS);
setup_clear_cpu_cap(X86_FEATURE_AVX512_VPOPCNTDQ);
--
2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
2017-10-20 0:08 [PATCH] x86/cpufeatures: Enable new AVX512 cpu features Gayatri Kammela
@ 2017-10-20 6:37 ` Thomas Gleixner
0 siblings, 0 replies; 7+ messages in thread
From: Thomas Gleixner @ 2017-10-20 6:37 UTC (permalink / raw)
To: Gayatri Kammela
Cc: LKML, x86, Borislav Petkov, hpa, Ravi Shankar, Fenghua Yu,
Ricardo Neri, Yang Zhong, Andi Kleen
On Thu, 19 Oct 2017, Gayatri Kammela wrote:
> @@ -76,6 +76,12 @@ void fpu__xstate_clear_all_cpu_caps(void)
> setup_clear_cpu_cap(X86_FEATURE_XGETBV1);
Please rework this against:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/fpu
Thanks,
tglx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
@ 2016-11-09 0:08 Gayatri Kammela
2016-11-09 9:19 ` Borislav Petkov
0 siblings, 1 reply; 7+ messages in thread
From: Gayatri Kammela @ 2016-11-09 0:08 UTC (permalink / raw)
To: mingo
Cc: linux-kernel, x86, Gayatri Kammela, H . Peter Anvin,
Ravi Shankar, Fenghua Yu
Modify cpufeatures.h to add new AVX512 instruction groups/features
for enuermation in /proc/cpuinfo: AVX512IFMA and AVX512VBMI
Also modify the xstate.c to clear the flags in
fpu__xstate_clear_all_cpu_caps().
CPUID.(EAX=7,ECX=0):EBX[bit 21] AVX512IFMA
CPUID.(Eax=7,ECX=0):ECX[bit 1] AVX512VBMI
Detailed information of cpuid bits for the features can be found in
Intel Architecture Instruction Set Extensions Programming Reference.
Cc: H. Peter Anvin <hpa@linux.intel.com>
Cc: Ravi Shankar <ravi.v.shankar@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/kernel/fpu/xstate.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 4a413485f9eb..c722fcc18a15 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -225,6 +225,7 @@
#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
+#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */
#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
@@ -279,6 +280,7 @@
#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */
+#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index 4ea2a59483c7..92411568e320 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -56,6 +56,7 @@ void fpu__xstate_clear_all_cpu_caps(void)
setup_clear_cpu_cap(X86_FEATURE_AVX);
setup_clear_cpu_cap(X86_FEATURE_AVX2);
setup_clear_cpu_cap(X86_FEATURE_AVX512F);
+ setup_clear_cpu_cap(X86_FEATURE_AVX512IFMA);
setup_clear_cpu_cap(X86_FEATURE_AVX512PF);
setup_clear_cpu_cap(X86_FEATURE_AVX512ER);
setup_clear_cpu_cap(X86_FEATURE_AVX512CD);
@@ -64,6 +65,7 @@ void fpu__xstate_clear_all_cpu_caps(void)
setup_clear_cpu_cap(X86_FEATURE_AVX512VL);
setup_clear_cpu_cap(X86_FEATURE_MPX);
setup_clear_cpu_cap(X86_FEATURE_XGETBV1);
+ setup_clear_cpu_cap(X86_FEATURE_AVX512VBMI);
setup_clear_cpu_cap(X86_FEATURE_PKU);
}
--
2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
2016-11-09 0:08 Gayatri Kammela
@ 2016-11-09 9:19 ` Borislav Petkov
2016-11-11 20:09 ` Kammela, Gayatri
0 siblings, 1 reply; 7+ messages in thread
From: Borislav Petkov @ 2016-11-09 9:19 UTC (permalink / raw)
To: Gayatri Kammela
Cc: mingo, linux-kernel, x86, H . Peter Anvin, Ravi Shankar, Fenghua Yu
On Tue, Nov 08, 2016 at 04:08:44PM -0800, Gayatri Kammela wrote:
> Modify cpufeatures.h to add new AVX512 instruction groups/features
> for enuermation in /proc/cpuinfo: AVX512IFMA and AVX512VBMI
>
> Also modify the xstate.c to clear the flags in
> fpu__xstate_clear_all_cpu_caps().
This is already visible in the diff itself, no need to explain what the
patch does.
Also, please run your commit message through a spellchecker.
> CPUID.(EAX=7,ECX=0):EBX[bit 21] AVX512IFMA
> CPUID.(Eax=7,ECX=0):ECX[bit 1] AVX512VBMI
s/Eax/EAX/
> Detailed information of cpuid bits for the features can be found in
> Intel Architecture Instruction Set Extensions Programming Reference.
We have recently started uploading such documents into
bugzilla.kernel.org in order to have a stable reference source, see
https://lkml.kernel.org/r/alpine.DEB.2.20.1611082002160.3501@nanos
Please do so too and add the link to the commit message.
Rest looks ok to me.
Thanks.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
^ permalink raw reply [flat|nested] 7+ messages in thread* RE: [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
2016-11-09 9:19 ` Borislav Petkov
@ 2016-11-11 20:09 ` Kammela, Gayatri
2016-11-15 12:02 ` Borislav Petkov
0 siblings, 1 reply; 7+ messages in thread
From: Kammela, Gayatri @ 2016-11-11 20:09 UTC (permalink / raw)
To: Borislav Petkov
Cc: mingo, linux-kernel, x86, H . Peter Anvin, Shankar, Ravi V, Yu, Fenghua
Hi Boris,
-----Original Message-----
From: Borislav Petkov [mailto:bp@alien8.de]
Sent: Wednesday, November 9, 2016 1:19 AM
To: Kammela, Gayatri <gayatri.kammela@intel.com>
Cc: mingo@elte.hu; linux-kernel@vger.kernel.org; x86@kernel.org; H . Peter Anvin <hpa@linux.intel.com>; Shankar, Ravi V <ravi.v.shankar@intel.com>; Yu, Fenghua <fenghua.yu@intel.com>
Subject: Re: [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
On Tue, Nov 08, 2016 at 04:08:44PM -0800, Gayatri Kammela wrote:
> Modify cpufeatures.h to add new AVX512 instruction groups/features for
> enuermation in /proc/cpuinfo: AVX512IFMA and AVX512VBMI
>
> Also modify the xstate.c to clear the flags in
> fpu__xstate_clear_all_cpu_caps().
>>This is already visible in the diff itself, no need to explain what the patch does.
Sure , I will make changes
>>Also, please run your commit message through a spellchecker.
My bad , thanks for letting me know!
> CPUID.(EAX=7,ECX=0):EBX[bit 21] AVX512IFMA CPUID.(Eax=7,ECX=0):ECX[bit
> 1] AVX512VBMI
>>s/Eax/EAX/
Sure
> Detailed information of cpuid bits for the features can be found in
> Intel Architecture Instruction Set Extensions Programming Reference.
>>We have recently started uploading such documents into bugzilla.kernel.org in order to have a stable reference source, see
>>https://lkml.kernel.org/r/alpine.DEB.2.20.1611082002160.3501@nanos
>>Please do so too and add the link to the commit message.
Since this is not bug or bug fix ,I am not sure under which product section in https://bugzilla.kernel.org/ should I upload the document for these two new features.
>>Rest looks ok to me.
>>Thanks.
>>--
>>Regards/Gruss,
>> Boris.
>>Good mailing practices for 400: avoid top-posting and trim the reply.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
2016-11-11 20:09 ` Kammela, Gayatri
@ 2016-11-15 12:02 ` Borislav Petkov
0 siblings, 0 replies; 7+ messages in thread
From: Borislav Petkov @ 2016-11-15 12:02 UTC (permalink / raw)
To: Kammela, Gayatri
Cc: mingo, linux-kernel, x86, H . Peter Anvin, Shankar, Ravi V, Yu, Fenghua
On Fri, Nov 11, 2016 at 08:09:04PM +0000, Kammela, Gayatri wrote:
> Since this is not bug or bug fix ,I am not sure under which product
> section in https://bugzilla.kernel.org/ should I upload the document
> for these two new features.
Just do what Kan has done here:
https://bugzilla.kernel.org/show_bug.cgi?id=187301
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
@ 2016-10-22 0:15 Gayatri Kammela
0 siblings, 0 replies; 7+ messages in thread
From: Gayatri Kammela @ 2016-10-22 0:15 UTC (permalink / raw)
To: linux-kernel; +Cc: Gayatri Kammela, Ravi Shankar, Fenghua Yu
Modify cpufeatures.h to add new AVX512 instruction groups/features
for enuermation in /proc/cpuinfo: AVX512IFMA and AVX512VBMI
Also modify the xstate.c to clear the flags in
fpu__xstate_clear_all_cpu_caps().
CPUID.(EAX=7,ECX=0):EBX[bit 21] AVX512IFMA
CPUID.(Eax=7,ECX=0):ECX[bit 1] AVX512VBMI
Detailed information of cpuid bits for the features can be found in
Intel Architecture Instruction Set Extensions Programming Reference.
Cc: Ravi Shankar <ravi.v.shankar@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/kernel/fpu/xstate.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 4a413485f9eb..c722fcc18a15 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -225,6 +225,7 @@
#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
+#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */
#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
@@ -279,6 +280,7 @@
#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */
+#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index 4ea2a59483c7..92411568e320 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -56,6 +56,7 @@ void fpu__xstate_clear_all_cpu_caps(void)
setup_clear_cpu_cap(X86_FEATURE_AVX);
setup_clear_cpu_cap(X86_FEATURE_AVX2);
setup_clear_cpu_cap(X86_FEATURE_AVX512F);
+ setup_clear_cpu_cap(X86_FEATURE_AVX512IFMA);
setup_clear_cpu_cap(X86_FEATURE_AVX512PF);
setup_clear_cpu_cap(X86_FEATURE_AVX512ER);
setup_clear_cpu_cap(X86_FEATURE_AVX512CD);
@@ -64,6 +65,7 @@ void fpu__xstate_clear_all_cpu_caps(void)
setup_clear_cpu_cap(X86_FEATURE_AVX512VL);
setup_clear_cpu_cap(X86_FEATURE_MPX);
setup_clear_cpu_cap(X86_FEATURE_XGETBV1);
+ setup_clear_cpu_cap(X86_FEATURE_AVX512VBMI);
setup_clear_cpu_cap(X86_FEATURE_PKU);
}
--
2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-10-20 6:37 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2017-10-20 0:08 [PATCH] x86/cpufeatures: Enable new AVX512 cpu features Gayatri Kammela
2017-10-20 6:37 ` Thomas Gleixner
-- strict thread matches above, loose matches on Subject: below --
2016-11-09 0:08 Gayatri Kammela
2016-11-09 9:19 ` Borislav Petkov
2016-11-11 20:09 ` Kammela, Gayatri
2016-11-15 12:02 ` Borislav Petkov
2016-10-22 0:15 Gayatri Kammela
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