[PATCH 0/2] mips: econet: add multi-vpe capability to EN751221

[PATCH 0/2] mips: econet: add multi-vpe capability to EN751221

[Caleb James DeLisle]

The EN751221 is a MIPS 34Kc so it supports MIPS_SMP_MT, but until now
this was disabled because to enable it requires the interrupt
controller to be in VEIC mode and previously only cascading mode was
supported by the interrupt controller driver. Since
commit 2ee2a685ee83 ("irqchip/econet-en751221: Support MIPS 34Kc VEIC mode")
the intc driver now supports VEIC mode. Add SMP_MT to init.c and
update the Device Tree to recognize dual VPE.

Caleb James DeLisle (2):
  mips: econet: add multi-vpe capability to EN751221
  mips: dts: econet: Describe dual-VPE 34Kc processor

 arch/mips/boot/dts/econet/en751221.dtsi |  7 +++++
 arch/mips/econet/Kconfig                |  4 +--
 arch/mips/econet/init.c                 | 42 ++++++++++++++++++++++++-
 3 files changed, 49 insertions(+), 4 deletions(-)


base-commit: 27c61f8565a438b2d1dea6f6a47af0e6dc12c112
-- 
2.39.5

[PATCH 1/2] mips: econet: add multi-vpe capability to EN751221

[Caleb James DeLisle]

EN751221 is a 34Kc so it has two VPEs (threads) but MIPS_SMP_MT
requires VEIC to be enabled in the interrupt controller, which only
became supported in
commit 2ee2a685ee83 ("irqchip/econet-en751221: Support MIPS 34Kc VEIC mode")

Register SMP_MT on startup and override init_secondary with CPU
interrupt unmasking as required by the EN751221 VEIC intc hardware.

Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
 arch/mips/econet/Kconfig |  4 +---
 arch/mips/econet/init.c  | 42 +++++++++++++++++++++++++++++++++++++++-
 2 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/arch/mips/econet/Kconfig b/arch/mips/econet/Kconfig
index b37b9d25d5a4..579fb5b01532 100644
--- a/arch/mips/econet/Kconfig
+++ b/arch/mips/econet/Kconfig
@@ -16,9 +16,7 @@ choice
 		select HAVE_PCI
 		select IRQ_MIPS_CPU
 		select PCI_DRIVERS_GENERIC
-		select SMP
-		select SMP_UP
-		select SYS_SUPPORTS_SMP
+		select SYS_SUPPORTS_MULTITHREADING
 		help
 		  The EN751221 family includes EN7512, RN7513, EN7521, EN7526.
 		  They are based on single core MIPS 34Kc processors. To boot
diff --git a/arch/mips/econet/init.c b/arch/mips/econet/init.c
index 6f43ffb209cb..ae45b8788504 100644
--- a/arch/mips/econet/init.c
+++ b/arch/mips/econet/init.c
@@ -28,6 +28,41 @@ static void hw_reset(char *command)
 	iowrite32(RESET, CR_AHB_RSTCR);
 }
 
+/*
+ * vsmp_init_secondary expects either GIC or cascading interrupt configuration.
+ * The EN751221 is a 34Kc with VEIC, but not GIC compatible. The cascading
+ * configuration enables lines 6 and 7 for performance counters, but when this
+ * is done on the EN751221 intc with VEIC enabled, it causes the whole intc to
+ * stop sending interrupts.
+ * Only unmask lines 0 and 1 (software interrupts) in init_secondary.
+ */
+#ifdef CONFIG_MIPS_MT_SMP
+extern const struct plat_smp_ops vsmp_smp_ops;
+static struct plat_smp_ops en75_smp_ops __ro_after_init;
+
+static void en751221_init_secondary(void)
+{
+	write_c0_status((read_c0_status() & ~ST0_IM) |
+		(STATUSF_IP0 | STATUSF_IP1));
+}
+
+static int __init en751221_register_vsmp_smp_ops(void)
+{
+	if (!cpu_has_mipsmt)
+		return -ENODEV;
+
+	en75_smp_ops = vsmp_smp_ops;
+	en75_smp_ops.init_secondary = en751221_init_secondary;
+	register_smp_ops(&en75_smp_ops);
+	return 0;
+}
+#else
+static int __init en751221_register_vsmp_smp_ops(void)
+{
+	return -ENODEV;
+}
+#endif /* CONFIG_MIPS_MT_SMP */
+
 /* 1. Bring up early printk. */
 void __init prom_init(void)
 {
@@ -51,11 +86,16 @@ void __init plat_mem_setup(void)
 	early_init_dt_scan_memory();
 }
 
-/* 3. Overload __weak device_tree_init(), add SMP_UP ops */
+/* 3. Overload __weak device_tree_init(), add SMP ops */
 void __init device_tree_init(void)
 {
 	unflatten_and_copy_device_tree();
 
+	/* EN751221 dual-vpe */
+	if (!en751221_register_vsmp_smp_ops())
+		return;
+
+	/* EN751221 with MT_SMP disabled */
 	register_up_smp_ops();
 }
 
-- 
2.39.5

[PATCH 2/2] mips: dts: econet: Describe dual-VPE 34Kc processor

[Caleb James DeLisle]

The 34Kc processor has two VPEs (threads) and the interrupt controller
on the EN751221 re-routes (in hardware) the software interrupt pins
zero and one to numbers 7 and 8 in the flat VEIC interrupt domain.

Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
 arch/mips/boot/dts/econet/en751221.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/mips/boot/dts/econet/en751221.dtsi b/arch/mips/boot/dts/econet/en751221.dtsi
index 72cb65654c34..57ae84a8a9f8 100644
--- a/arch/mips/boot/dts/econet/en751221.dtsi
+++ b/arch/mips/boot/dts/econet/en751221.dtsi
@@ -23,6 +23,12 @@ cpu@0 {
 			compatible = "mips,mips34Kc";
 			reg = <0>;
 		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "mips,mips34Kc";
+			reg = <1>;
+		};
 	};
 
 	cpuintc: interrupt-controller {
@@ -65,6 +71,7 @@ intc: interrupt-controller@1fb40000 {
 		interrupt-controller;
 		#interrupt-cells = <1>;
 		econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
+		econet,cpu-interrupt-map = <7 0>, <8 1>;
 	};
 
 	pciecfg: pciecfg@1fb80000 {
-- 
2.39.5

Re: [PATCH 0/2] mips: econet: add multi-vpe capability to EN751221

[Thomas Bogendoerfer]

On Tue, Jul 28, 2026 at 06:49:57PM +0000, Caleb James DeLisle wrote:
> The EN751221 is a MIPS 34Kc so it supports MIPS_SMP_MT, but until now
> this was disabled because to enable it requires the interrupt
> controller to be in VEIC mode and previously only cascading mode was
> supported by the interrupt controller driver. Since
> commit 2ee2a685ee83 ("irqchip/econet-en751221: Support MIPS 34Kc VEIC mode")
> the intc driver now supports VEIC mode. Add SMP_MT to init.c and
> update the Device Tree to recognize dual VPE.
> 
> Caleb James DeLisle (2):
>   mips: econet: add multi-vpe capability to EN751221
>   mips: dts: econet: Describe dual-VPE 34Kc processor
> 
>  arch/mips/boot/dts/econet/en751221.dtsi |  7 +++++
>  arch/mips/econet/Kconfig                |  4 +--
>  arch/mips/econet/init.c                 | 42 ++++++++++++++++++++++++-
>  3 files changed, 49 insertions(+), 4 deletions(-)

series applied to mips-next

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
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