[PATCH] spi: realtek-rtl: add support for second CS

[PATCH] spi: realtek-rtl: add support for second CS

[Jonas Jelonek]

The initial driver assumed that the controller's second chip select was
vestigial because none of the devices examined at the time used it. This
does not hold for all hardware: there are devices with a peripheral
connected to CS1. Since the controller only advertises one chip select
and keeps CS1 permanently deasserted, those peripherals cannot be used.

Advertise both native chip selects, select the appropriate CSBx register
bit in ->set_cs(), and leave both lines deasserted after initialization.

Rename the callback argument from "active" to "level" while touching this
code. ->set_cs() receives the physical line level, not a logical assertion
state: after applying SPI_CS_HIGH, the core passes false to drive the line
low and true to drive it high. The CSBx bits directly encode that level,
and the native outputs are active-low, so clear the selected bit for a
low/asserted line and set it for a high/deasserted line.

Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
---
 drivers/spi/spi-realtek-rtl.c | 33 +++++++++++++++++++++++----------
 1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/spi-realtek-rtl.c b/drivers/spi/spi-realtek-rtl.c
index e1c40ff2e49d..f382f3d428df 100644
--- a/drivers/spi/spi-realtek-rtl.c
+++ b/drivers/spi/spi-realtek-rtl.c
@@ -29,17 +29,31 @@ struct rtspi {
 #define REG(x)		(rtspi->base + x)
 
 
-static void rt_set_cs(struct spi_device *spi, bool active)
+static void rt_set_cs(struct spi_device *spi, bool level)
 {
 	struct rtspi *rtspi = spi_controller_get_devdata(spi->controller);
-	u32 value;
+	unsigned int cs = spi_get_chipselect(spi, 0);
+	u32 cs_mask, value;
+
+	switch (cs) {
+	case 0:
+		cs_mask = RTL_SPI_SFCSR_CSB0;
+		break;
+	case 1:
+		cs_mask = RTL_SPI_SFCSR_CSB1;
+		break;
+	default:
+		return;
+	}
 
-	/* CS0 bit is active low */
 	value = __raw_readl(REG(RTL_SPI_SFCSR));
-	if (active)
-		value |= RTL_SPI_SFCSR_CSB0;
+
+	/* CSBx is active low */
+	if (level)
+		value |= cs_mask;
 	else
-		value &= ~RTL_SPI_SFCSR_CSB0;
+		value &= ~cs_mask;
+
 	__raw_writel(value, REG(RTL_SPI_SFCSR));
 }
 
@@ -138,11 +152,9 @@ static void init_hw(struct rtspi *rtspi)
 	value |= RTL_SPI_SFCR_RBO | RTL_SPI_SFCR_WBO;
 	__raw_writel(value, REG(RTL_SPI_SFCR));
 
+	/* CSB0/CSB1 are active low: deassert both. */
 	value = __raw_readl(REG(RTL_SPI_SFCSR));
-	/* Permanently disable CS1, since it's never used */
-	value |= RTL_SPI_SFCSR_CSB1;
-	/* Select CS0 for use */
-	value &= RTL_SPI_SFCSR_CS;
+	value |= RTL_SPI_SFCSR_CSB0 | RTL_SPI_SFCSR_CSB1;
 	__raw_writel(value, REG(RTL_SPI_SFCSR));
 }
 
@@ -171,6 +183,7 @@ static int realtek_rtl_spi_probe(struct platform_device *pdev)
 	ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
 	ctrl->set_cs = rt_set_cs;
 	ctrl->transfer_one = transfer_one;
+	ctrl->num_chipselect = 2;
 
 	err = devm_spi_register_controller(&pdev->dev, ctrl);
 	if (err) {

base-commit: 531c719eaeff3ee12af85ccd259f60846214074c
-- 
2.53.0

Re: [PATCH] spi: realtek-rtl: add support for second CS

[Mark Brown]

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On Fri, Sep 18, 2026 at 09:47:40PM +0000, Jonas Jelonek wrote:
> The initial driver assumed that the controller's second chip select was
> vestigial because none of the devices examined at the time used it. This
> does not hold for all hardware: there are devices with a peripheral
> connected to CS1. Since the controller only advertises one chip select
> and keeps CS1 permanently deasserted, those peripherals cannot be used.

> +	/* CSB0/CSB1 are active low: deassert both. */
>  	value = __raw_readl(REG(RTL_SPI_SFCSR));
> -	/* Permanently disable CS1, since it's never used */
> -	value |= RTL_SPI_SFCSR_CSB1;
> -	/* Select CS0 for use */
> -	value &= RTL_SPI_SFCSR_CS;
> +	value |= RTL_SPI_SFCSR_CSB0 | RTL_SPI_SFCSR_CSB1;
>  	__raw_writel(value, REG(RTL_SPI_SFCSR));

The original code would ensure that all bits in the register are
initialised to known values, the new code sets some bits and leaves the
rest with whatever value they happened to have previously.  Probably we
still want the initialisation of the other bits.

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Re: [PATCH] spi: realtek-rtl: add support for second CS

[Jonas Jelonek]

Hi,

On 19.09.26 18:46, Mark Brown wrote:
> On Fri, Sep 18, 2026 at 09:47:40PM +0000, Jonas Jelonek wrote:
>> The initial driver assumed that the controller's second chip select was
>> vestigial because none of the devices examined at the time used it. This
>> does not hold for all hardware: there are devices with a peripheral
>> connected to CS1. Since the controller only advertises one chip select
>> and keeps CS1 permanently deasserted, those peripherals cannot be used.
>> +	/* CSB0/CSB1 are active low: deassert both. */
>>  	value = __raw_readl(REG(RTL_SPI_SFCSR));
>> -	/* Permanently disable CS1, since it's never used */
>> -	value |= RTL_SPI_SFCSR_CSB1;
>> -	/* Select CS0 for use */
>> -	value &= RTL_SPI_SFCSR_CS;
>> +	value |= RTL_SPI_SFCSR_CSB0 | RTL_SPI_SFCSR_CSB1;
>>  	__raw_writel(value, REG(RTL_SPI_SFCSR));
> The original code would ensure that all bits in the register are
> initialised to known values, the new code sets some bits and leaves the
> rest with whatever value they happened to have previously.  Probably we
> still want the initialisation of the other bits.

Yes, you're right. Thanks for pointing that out. Indeed, bits setting the
data length and the I/O mode sit in this register too. Zero is required to
have one byte data length and single I/O. I'll fix this in a v2.

Best,
Jonas