* [PATCH v3 01/10] ufs: unipro: Move Tx/Rx FSM state definitions to unipro.h
2026-09-16 8:44 [PATCH v3 00/10] Add S32N79RDB UFS support Larisa Grigore
@ 2026-09-16 8:44 ` Larisa Grigore
2026-09-16 16:14 ` Frank Li
2026-09-16 8:44 ` [PATCH v3 02/10] ufs: unipro: Add TX/RX FSM state attributes Larisa Grigore
` (8 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Larisa Grigore @ 2026-09-16 8:44 UTC (permalink / raw)
To: Larisa Grigore, NXP S32 Linux Team, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa
Cc: linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
Move the Tx/Rx FSM state definitions from ufshcd-dwc.h to
include/ufs/unipro.h.
These state values are UniPro/M-PHY related and are not specific to
the DesignWare UFS host controller implementation, so unipro.h is a
more appropriate location for sharing them.
As part of this move, drop the driver-private TX_FSM_HIBERN8 define in
ufs-hisi and ufs-qcom and repoint their Hibern8 checks at the shared
TX_STATE_HIBERN8 enum constant. This is a no-op change: TX_FSM_HIBERN8
was 0x1 and TX_STATE_HIBERN8 is 1, so the compared values are identical.
This also prepares for using these definitions in a subsequent commit.
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
---
drivers/ufs/host/ufs-hisi.c | 8 ++++----
drivers/ufs/host/ufs-hisi.h | 1 -
drivers/ufs/host/ufs-qcom.c | 4 ++--
drivers/ufs/host/ufs-qcom.h | 1 -
drivers/ufs/host/ufshcd-dwc.h | 19 -------------------
include/ufs/unipro.h | 20 ++++++++++++++++++++
6 files changed, 26 insertions(+), 27 deletions(-)
diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
index 993e20ac211d..2d214ce9620e 100644
--- a/drivers/ufs/host/ufs-hisi.c
+++ b/drivers/ufs/host/ufs-hisi.c
@@ -34,8 +34,8 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
&tx_fsm_val_0);
err |= ufshcd_dme_get(hba,
UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
- if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 &&
- tx_fsm_val_1 == TX_FSM_HIBERN8))
+ if (err || (tx_fsm_val_0 == TX_STATE_HIBERN8 &&
+ tx_fsm_val_1 == TX_STATE_HIBERN8))
break;
/* sleep for max. 200us */
@@ -56,8 +56,8 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
if (err) {
dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
__func__, err);
- } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 ||
- tx_fsm_val_1 != TX_FSM_HIBERN8) {
+ } else if (tx_fsm_val_0 != TX_STATE_HIBERN8 ||
+ tx_fsm_val_1 != TX_STATE_HIBERN8) {
err = -1;
dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n",
__func__, tx_fsm_val_0, tx_fsm_val_1);
diff --git a/drivers/ufs/host/ufs-hisi.h b/drivers/ufs/host/ufs-hisi.h
index 5a90c0f4e90c..6af6a268458d 100644
--- a/drivers/ufs/host/ufs-hisi.h
+++ b/drivers/ufs/host/ufs-hisi.h
@@ -43,7 +43,6 @@
* M-TX Configuration Attributes for Hixxxx
*/
#define MPHY_TX_FSM_STATE 0x41
-#define TX_FSM_HIBERN8 0x1
/*
* Hixxxx UFS HC specific Registers
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 954be9343f42..38897d01fde2 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -393,7 +393,7 @@ static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
&tx_fsm_val);
- if (err || tx_fsm_val == TX_FSM_HIBERN8)
+ if (err || tx_fsm_val == TX_STATE_HIBERN8)
break;
/* sleep for max. 200us */
@@ -413,7 +413,7 @@ static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
if (err) {
dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
__func__, err);
- } else if (tx_fsm_val != TX_FSM_HIBERN8) {
+ } else if (tx_fsm_val != TX_STATE_HIBERN8) {
err = tx_fsm_val;
dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
__func__, err);
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index a5ad5ce44a19..3c6cb2281af0 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -11,7 +11,6 @@
#include <ufs/ufshcd.h>
#define MPHY_TX_FSM_STATE 0x41
-#define TX_FSM_HIBERN8 0x1
#define HBRN8_POLL_TOUT_MS 100
#define DEFAULT_CLK_RATE_HZ 1000000
#define MAX_SUPP_MAC 64
diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h
index c618bb914904..a5e40e7604a1 100644
--- a/drivers/ufs/host/ufshcd-dwc.h
+++ b/drivers/ufs/host/ufshcd-dwc.h
@@ -39,25 +39,6 @@
#define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100))
#define FW_CALIB_CCFG(n) (0x404D + ((n) * 0x100))
-/* Tx/Rx FSM state */
-enum rx_fsm_state {
- RX_STATE_DISABLED = 0,
- RX_STATE_HIBERN8 = 1,
- RX_STATE_SLEEP = 2,
- RX_STATE_STALL = 3,
- RX_STATE_LSBURST = 4,
- RX_STATE_HSBURST = 5,
-};
-
-enum tx_fsm_state {
- TX_STATE_DISABLED = 0,
- TX_STATE_HIBERN8 = 1,
- TX_STATE_SLEEP = 2,
- TX_STATE_STALL = 3,
- TX_STATE_LSBURST = 4,
- TX_STATE_HSBURST = 5,
-};
-
struct ufshcd_dme_attr_val {
u32 attr_sel;
u32 mib_val;
diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h
index 9c168703b104..e0f490e11c7f 100644
--- a/include/ufs/unipro.h
+++ b/include/ufs/unipro.h
@@ -466,4 +466,24 @@ enum {
CPORT_CONNECTED,
};
+/* RX_FSM_State encoding, MIPI M-PHY v6.0 Table 50 (M-RX Status Attributes) */
+enum ufs_rx_fsm_state {
+ RX_STATE_DISABLED = 0,
+ RX_STATE_HIBERN8 = 1,
+ RX_STATE_SLEEP = 2,
+ RX_STATE_STALL = 3,
+ RX_STATE_LSBURST = 4,
+ RX_STATE_HSBURST = 5,
+};
+
+/* TX_FSM_State encoding, MIPI M-PHY v6.0 Table 47 (M-TX Status Attributes) */
+enum ufs_tx_fsm_state {
+ TX_STATE_DISABLED = 0,
+ TX_STATE_HIBERN8 = 1,
+ TX_STATE_SLEEP = 2,
+ TX_STATE_STALL = 3,
+ TX_STATE_LSBURST = 4,
+ TX_STATE_HSBURST = 5,
+};
+
#endif /* _UNIPRO_H_ */
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 01/10] ufs: unipro: Move Tx/Rx FSM state definitions to unipro.h
2026-09-16 8:44 ` [PATCH v3 01/10] ufs: unipro: Move Tx/Rx FSM state definitions to unipro.h Larisa Grigore
@ 2026-09-16 16:14 ` Frank Li
2026-09-17 9:00 ` Larisa Ileana Grigore
0 siblings, 1 reply; 17+ messages in thread
From: Frank Li @ 2026-09-16 16:14 UTC (permalink / raw)
To: Larisa Grigore
Cc: NXP S32 Linux Team, Alim Akhtar, Avri Altman, Bart Van Assche,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa ,
linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
On Wed, Sep 16, 2026 at 10:44:02AM +0200, Larisa Grigore wrote:
> Move the Tx/Rx FSM state definitions from ufshcd-dwc.h to
> include/ufs/unipro.h.
>
> These state values are UniPro/M-PHY related and are not specific to
> the DesignWare UFS host controller implementation, so unipro.h is a
> more appropriate location for sharing them.
>
> As part of this move, drop the driver-private TX_FSM_HIBERN8 define in
> ufs-hisi and ufs-qcom and repoint their Hibern8 checks at the shared
> TX_STATE_HIBERN8 enum constant. This is a no-op change: TX_FSM_HIBERN8
> was 0x1 and TX_STATE_HIBERN8 is 1, so the compared values are identical.
>
> This also prepares for using these definitions in a subsequent commit.
>
> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/ufs/host/ufs-hisi.c | 8 ++++----
> drivers/ufs/host/ufs-hisi.h | 1 -
> drivers/ufs/host/ufs-qcom.c | 4 ++--
> drivers/ufs/host/ufs-qcom.h | 1 -
> drivers/ufs/host/ufshcd-dwc.h | 19 -------------------
> include/ufs/unipro.h | 20 ++++++++++++++++++++
> 6 files changed, 26 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
> index 993e20ac211d..2d214ce9620e 100644
> --- a/drivers/ufs/host/ufs-hisi.c
> +++ b/drivers/ufs/host/ufs-hisi.c
> @@ -34,8 +34,8 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
> &tx_fsm_val_0);
> err |= ufshcd_dme_get(hba,
> UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
> - if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 &&
> - tx_fsm_val_1 == TX_FSM_HIBERN8))
> + if (err || (tx_fsm_val_0 == TX_STATE_HIBERN8 &&
> + tx_fsm_val_1 == TX_STATE_HIBERN8))
> break;
>
> /* sleep for max. 200us */
> @@ -56,8 +56,8 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
> if (err) {
> dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
> __func__, err);
> - } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 ||
> - tx_fsm_val_1 != TX_FSM_HIBERN8) {
> + } else if (tx_fsm_val_0 != TX_STATE_HIBERN8 ||
> + tx_fsm_val_1 != TX_STATE_HIBERN8) {
> err = -1;
> dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n",
> __func__, tx_fsm_val_0, tx_fsm_val_1);
> diff --git a/drivers/ufs/host/ufs-hisi.h b/drivers/ufs/host/ufs-hisi.h
> index 5a90c0f4e90c..6af6a268458d 100644
> --- a/drivers/ufs/host/ufs-hisi.h
> +++ b/drivers/ufs/host/ufs-hisi.h
> @@ -43,7 +43,6 @@
> * M-TX Configuration Attributes for Hixxxx
> */
> #define MPHY_TX_FSM_STATE 0x41
> -#define TX_FSM_HIBERN8 0x1
>
> /*
> * Hixxxx UFS HC specific Registers
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 954be9343f42..38897d01fde2 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -393,7 +393,7 @@ static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
> UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
> UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
> &tx_fsm_val);
> - if (err || tx_fsm_val == TX_FSM_HIBERN8)
> + if (err || tx_fsm_val == TX_STATE_HIBERN8)
> break;
>
> /* sleep for max. 200us */
> @@ -413,7 +413,7 @@ static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
> if (err) {
> dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
> __func__, err);
> - } else if (tx_fsm_val != TX_FSM_HIBERN8) {
> + } else if (tx_fsm_val != TX_STATE_HIBERN8) {
> err = tx_fsm_val;
> dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
> __func__, err);
> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
> index a5ad5ce44a19..3c6cb2281af0 100644
> --- a/drivers/ufs/host/ufs-qcom.h
> +++ b/drivers/ufs/host/ufs-qcom.h
> @@ -11,7 +11,6 @@
> #include <ufs/ufshcd.h>
>
> #define MPHY_TX_FSM_STATE 0x41
> -#define TX_FSM_HIBERN8 0x1
> #define HBRN8_POLL_TOUT_MS 100
> #define DEFAULT_CLK_RATE_HZ 1000000
> #define MAX_SUPP_MAC 64
> diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h
> index c618bb914904..a5e40e7604a1 100644
> --- a/drivers/ufs/host/ufshcd-dwc.h
> +++ b/drivers/ufs/host/ufshcd-dwc.h
> @@ -39,25 +39,6 @@
> #define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100))
> #define FW_CALIB_CCFG(n) (0x404D + ((n) * 0x100))
>
> -/* Tx/Rx FSM state */
> -enum rx_fsm_state {
> - RX_STATE_DISABLED = 0,
> - RX_STATE_HIBERN8 = 1,
> - RX_STATE_SLEEP = 2,
> - RX_STATE_STALL = 3,
> - RX_STATE_LSBURST = 4,
> - RX_STATE_HSBURST = 5,
> -};
> -
> -enum tx_fsm_state {
> - TX_STATE_DISABLED = 0,
> - TX_STATE_HIBERN8 = 1,
> - TX_STATE_SLEEP = 2,
> - TX_STATE_STALL = 3,
> - TX_STATE_LSBURST = 4,
> - TX_STATE_HSBURST = 5,
> -};
> -
> struct ufshcd_dme_attr_val {
> u32 attr_sel;
> u32 mib_val;
> diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h
> index 9c168703b104..e0f490e11c7f 100644
> --- a/include/ufs/unipro.h
> +++ b/include/ufs/unipro.h
> @@ -466,4 +466,24 @@ enum {
> CPORT_CONNECTED,
> };
>
> +/* RX_FSM_State encoding, MIPI M-PHY v6.0 Table 50 (M-RX Status Attributes) */
> +enum ufs_rx_fsm_state {
> + RX_STATE_DISABLED = 0,
> + RX_STATE_HIBERN8 = 1,
> + RX_STATE_SLEEP = 2,
> + RX_STATE_STALL = 3,
> + RX_STATE_LSBURST = 4,
> + RX_STATE_HSBURST = 5,
> +};
> +
> +/* TX_FSM_State encoding, MIPI M-PHY v6.0 Table 47 (M-TX Status Attributes) */
> +enum ufs_tx_fsm_state {
> + TX_STATE_DISABLED = 0,
> + TX_STATE_HIBERN8 = 1,
> + TX_STATE_SLEEP = 2,
> + TX_STATE_STALL = 3,
> + TX_STATE_LSBURST = 4,
> + TX_STATE_HSBURST = 5,
> +};
> +
> #endif /* _UNIPRO_H_ */
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 01/10] ufs: unipro: Move Tx/Rx FSM state definitions to unipro.h
2026-09-16 16:14 ` Frank Li
@ 2026-09-17 9:00 ` Larisa Ileana Grigore
0 siblings, 0 replies; 17+ messages in thread
From: Larisa Ileana Grigore @ 2026-09-17 9:00 UTC (permalink / raw)
To: Frank Li
Cc: NXP S32 Linux Team, Alim Akhtar, Avri Altman, Bart Van Assche,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa, linux-scsi,
devicetree, linux-kernel, imx, linux-arm-kernel, linux-arm-msm,
clizzi, aruizrui, eballetb, echanude
On 9/16/2026 7:14 PM, Frank Li wrote:
> On Wed, Sep 16, 2026 at 10:44:02AM +0200, Larisa Grigore wrote:
>> Move the Tx/Rx FSM state definitions from ufshcd-dwc.h to
>> include/ufs/unipro.h.
>>
>> These state values are UniPro/M-PHY related and are not specific to
>> the DesignWare UFS host controller implementation, so unipro.h is a
>> more appropriate location for sharing them.
>>
>> As part of this move, drop the driver-private TX_FSM_HIBERN8 define in
>> ufs-hisi and ufs-qcom and repoint their Hibern8 checks at the shared
>> TX_STATE_HIBERN8 enum constant. This is a no-op change: TX_FSM_HIBERN8
>> was 0x1 and TX_STATE_HIBERN8 is 1, so the compared values are identical.
>>
>> This also prepares for using these definitions in a subsequent commit.
>>
>> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
>> ---
>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
Thank you!
>> drivers/ufs/host/ufs-hisi.c | 8 ++++----
>> drivers/ufs/host/ufs-hisi.h | 1 -
>> drivers/ufs/host/ufs-qcom.c | 4 ++--
>> drivers/ufs/host/ufs-qcom.h | 1 -
>> drivers/ufs/host/ufshcd-dwc.h | 19 -------------------
>> include/ufs/unipro.h | 20 ++++++++++++++++++++
>> 6 files changed, 26 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
>> index 993e20ac211d..2d214ce9620e 100644
>> --- a/drivers/ufs/host/ufs-hisi.c
>> +++ b/drivers/ufs/host/ufs-hisi.c
>> @@ -34,8 +34,8 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
>> &tx_fsm_val_0);
>> err |= ufshcd_dme_get(hba,
>> UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
>> - if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 &&
>> - tx_fsm_val_1 == TX_FSM_HIBERN8))
>> + if (err || (tx_fsm_val_0 == TX_STATE_HIBERN8 &&
>> + tx_fsm_val_1 == TX_STATE_HIBERN8))
>> break;
>>
>> /* sleep for max. 200us */
>> @@ -56,8 +56,8 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
>> if (err) {
>> dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
>> __func__, err);
>> - } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 ||
>> - tx_fsm_val_1 != TX_FSM_HIBERN8) {
>> + } else if (tx_fsm_val_0 != TX_STATE_HIBERN8 ||
>> + tx_fsm_val_1 != TX_STATE_HIBERN8) {
>> err = -1;
>> dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n",
>> __func__, tx_fsm_val_0, tx_fsm_val_1);
>> diff --git a/drivers/ufs/host/ufs-hisi.h b/drivers/ufs/host/ufs-hisi.h
>> index 5a90c0f4e90c..6af6a268458d 100644
>> --- a/drivers/ufs/host/ufs-hisi.h
>> +++ b/drivers/ufs/host/ufs-hisi.h
>> @@ -43,7 +43,6 @@
>> * M-TX Configuration Attributes for Hixxxx
>> */
>> #define MPHY_TX_FSM_STATE 0x41
>> -#define TX_FSM_HIBERN8 0x1
>>
>> /*
>> * Hixxxx UFS HC specific Registers
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index 954be9343f42..38897d01fde2 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -393,7 +393,7 @@ static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
>> UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
>> UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
>> &tx_fsm_val);
>> - if (err || tx_fsm_val == TX_FSM_HIBERN8)
>> + if (err || tx_fsm_val == TX_STATE_HIBERN8)
>> break;
>>
>> /* sleep for max. 200us */
>> @@ -413,7 +413,7 @@ static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
>> if (err) {
>> dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
>> __func__, err);
>> - } else if (tx_fsm_val != TX_FSM_HIBERN8) {
>> + } else if (tx_fsm_val != TX_STATE_HIBERN8) {
>> err = tx_fsm_val;
>> dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
>> __func__, err);
>> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
>> index a5ad5ce44a19..3c6cb2281af0 100644
>> --- a/drivers/ufs/host/ufs-qcom.h
>> +++ b/drivers/ufs/host/ufs-qcom.h
>> @@ -11,7 +11,6 @@
>> #include <ufs/ufshcd.h>
>>
>> #define MPHY_TX_FSM_STATE 0x41
>> -#define TX_FSM_HIBERN8 0x1
>> #define HBRN8_POLL_TOUT_MS 100
>> #define DEFAULT_CLK_RATE_HZ 1000000
>> #define MAX_SUPP_MAC 64
>> diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h
>> index c618bb914904..a5e40e7604a1 100644
>> --- a/drivers/ufs/host/ufshcd-dwc.h
>> +++ b/drivers/ufs/host/ufshcd-dwc.h
>> @@ -39,25 +39,6 @@
>> #define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100))
>> #define FW_CALIB_CCFG(n) (0x404D + ((n) * 0x100))
>>
>> -/* Tx/Rx FSM state */
>> -enum rx_fsm_state {
>> - RX_STATE_DISABLED = 0,
>> - RX_STATE_HIBERN8 = 1,
>> - RX_STATE_SLEEP = 2,
>> - RX_STATE_STALL = 3,
>> - RX_STATE_LSBURST = 4,
>> - RX_STATE_HSBURST = 5,
>> -};
>> -
>> -enum tx_fsm_state {
>> - TX_STATE_DISABLED = 0,
>> - TX_STATE_HIBERN8 = 1,
>> - TX_STATE_SLEEP = 2,
>> - TX_STATE_STALL = 3,
>> - TX_STATE_LSBURST = 4,
>> - TX_STATE_HSBURST = 5,
>> -};
>> -
>> struct ufshcd_dme_attr_val {
>> u32 attr_sel;
>> u32 mib_val;
>> diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h
>> index 9c168703b104..e0f490e11c7f 100644
>> --- a/include/ufs/unipro.h
>> +++ b/include/ufs/unipro.h
>> @@ -466,4 +466,24 @@ enum {
>> CPORT_CONNECTED,
>> };
>>
>> +/* RX_FSM_State encoding, MIPI M-PHY v6.0 Table 50 (M-RX Status Attributes) */
>> +enum ufs_rx_fsm_state {
>> + RX_STATE_DISABLED = 0,
>> + RX_STATE_HIBERN8 = 1,
>> + RX_STATE_SLEEP = 2,
>> + RX_STATE_STALL = 3,
>> + RX_STATE_LSBURST = 4,
>> + RX_STATE_HSBURST = 5,
>> +};
>> +
>> +/* TX_FSM_State encoding, MIPI M-PHY v6.0 Table 47 (M-TX Status Attributes) */
>> +enum ufs_tx_fsm_state {
>> + TX_STATE_DISABLED = 0,
>> + TX_STATE_HIBERN8 = 1,
>> + TX_STATE_SLEEP = 2,
>> + TX_STATE_STALL = 3,
>> + TX_STATE_LSBURST = 4,
>> + TX_STATE_HSBURST = 5,
>> +};
>> +
>> #endif /* _UNIPRO_H_ */
>> --
>> 2.43.0
>>
>>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 02/10] ufs: unipro: Add TX/RX FSM state attributes
2026-09-16 8:44 [PATCH v3 00/10] Add S32N79RDB UFS support Larisa Grigore
2026-09-16 8:44 ` [PATCH v3 01/10] ufs: unipro: Move Tx/Rx FSM state definitions to unipro.h Larisa Grigore
@ 2026-09-16 8:44 ` Larisa Grigore
2026-09-16 8:44 ` [PATCH v3 03/10] ufs: host: Add common Hibern8 TX FSM polling helper Larisa Grigore
` (7 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Larisa Grigore @ 2026-09-16 8:44 UTC (permalink / raw)
To: Larisa Grigore, NXP S32 Linux Team, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa
Cc: linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
Add TX_FSM_STATE and RX_FSM_STATE to include/ufs/unipro.h, as these are
UniPro M-PHY attribute definitions rather than host controller specific
ones.
Remove the duplicated local definitions from the HiSilicon, Qualcomm, AMD
Versal and DesignWare UFS headers.
This also prepares for using these definitions in a subsequent commit.
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
drivers/ufs/host/ufs-amd-versal2.c | 4 ++--
drivers/ufs/host/ufs-hisi.c | 8 ++++----
drivers/ufs/host/ufs-hisi.h | 5 -----
drivers/ufs/host/ufs-qcom.c | 4 ++--
drivers/ufs/host/ufs-qcom.h | 1 -
drivers/ufs/host/ufshcd-dwc.h | 4 ----
include/ufs/unipro.h | 2 ++
7 files changed, 10 insertions(+), 18 deletions(-)
diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c
index 2154d6286817..0d4d5e98ad65 100644
--- a/drivers/ufs/host/ufs-amd-versal2.c
+++ b/drivers/ufs/host/ufs-amd-versal2.c
@@ -112,7 +112,7 @@ static int ufs_versal2_enable_phy(struct ufs_hba *hba)
u32 time_left, mibsel;
time_left = TIMEOUT_MICROSEC;
- mibsel = UIC_ARG_MIB_SEL(MTX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(offset));
+ mibsel = UIC_ARG_MIB_SEL(TX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(offset));
do {
ret = ufshcd_dme_get(hba, mibsel, ®);
if (ret)
@@ -132,7 +132,7 @@ static int ufs_versal2_enable_phy(struct ufs_hba *hba)
}
time_left = TIMEOUT_MICROSEC;
- mibsel = UIC_ARG_MIB_SEL(MRX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(offset));
+ mibsel = UIC_ARG_MIB_SEL(RX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(offset));
do {
ret = ufshcd_dme_get(hba, mibsel, ®);
if (ret)
diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
index 2d214ce9620e..bd223bda1ce2 100644
--- a/drivers/ufs/host/ufs-hisi.c
+++ b/drivers/ufs/host/ufs-hisi.c
@@ -30,10 +30,10 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
do {
- err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
+ err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(TX_FSM_STATE, 0),
&tx_fsm_val_0);
err |= ufshcd_dme_get(hba,
- UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
+ UIC_ARG_MIB_SEL(TX_FSM_STATE, 1), &tx_fsm_val_1);
if (err || (tx_fsm_val_0 == TX_STATE_HIBERN8 &&
tx_fsm_val_1 == TX_STATE_HIBERN8))
break;
@@ -47,10 +47,10 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
* check the state again.
*/
if (time_after(jiffies, timeout)) {
- err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
+ err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(TX_FSM_STATE, 0),
&tx_fsm_val_0);
err |= ufshcd_dme_get(hba,
- UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
+ UIC_ARG_MIB_SEL(TX_FSM_STATE, 1), &tx_fsm_val_1);
}
if (err) {
diff --git a/drivers/ufs/host/ufs-hisi.h b/drivers/ufs/host/ufs-hisi.h
index 6af6a268458d..08dccfbec404 100644
--- a/drivers/ufs/host/ufs-hisi.h
+++ b/drivers/ufs/host/ufs-hisi.h
@@ -39,11 +39,6 @@
#define MASK_UFS_DEVICE_RESET (0x1 << 16)
#define BIT_UFS_DEVICE_RESET (0x1)
-/*
- * M-TX Configuration Attributes for Hixxxx
- */
-#define MPHY_TX_FSM_STATE 0x41
-
/*
* Hixxxx UFS HC specific Registers
*/
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 38897d01fde2..1e492dac8d93 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -390,7 +390,7 @@ static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
do {
err = ufshcd_dme_get(hba,
- UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
+ UIC_ARG_MIB_SEL(TX_FSM_STATE,
UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
&tx_fsm_val);
if (err || tx_fsm_val == TX_STATE_HIBERN8)
@@ -406,7 +406,7 @@ static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
*/
if (time_after(jiffies, timeout))
err = ufshcd_dme_get(hba,
- UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
+ UIC_ARG_MIB_SEL(TX_FSM_STATE,
UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
&tx_fsm_val);
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 3c6cb2281af0..1ec661277c1d 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -10,7 +10,6 @@
#include <soc/qcom/ice.h>
#include <ufs/ufshcd.h>
-#define MPHY_TX_FSM_STATE 0x41
#define HBRN8_POLL_TOUT_MS 100
#define DEFAULT_CLK_RATE_HZ 1000000
#define MAX_SUPP_MAC 64
diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h
index a5e40e7604a1..0406f2bb576b 100644
--- a/drivers/ufs/host/ufshcd-dwc.h
+++ b/drivers/ufs/host/ufshcd-dwc.h
@@ -27,10 +27,6 @@
#define CBREFREFCLK_GATE_OVR_EN BIT(7)
-/* M-PHY Attributes */
-#define MTX_FSM_STATE 0x41
-#define MRX_FSM_STATE 0xC1
-
/* M-PHY registers */
#define RX_OVRD_IN_1(n) (0x3006 + ((n) * 0x100))
#define RX_PCS_OUT(n) (0x300F + ((n) * 0x100))
diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h
index e0f490e11c7f..6fee545bdee5 100644
--- a/include/ufs/unipro.h
+++ b/include/ufs/unipro.h
@@ -34,6 +34,7 @@
#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
#define TX_HS_DEEMPHASIS_SETTING 0x0037
#define TX_HS_PRESHOOT_SETTING 0x003B
+#define TX_FSM_STATE 0x0041
#define TX_REFCLKFREQ 0x00EB
#define TX_CFGCLKFREQVAL 0x00EC
#define CFGEXTRATTR 0x00F0
@@ -72,6 +73,7 @@
#define CFGRXCDR8 0x00BA
#define CFGRXOVR8 0x00BD
#define CFGRXOVR6 0x00BF
+#define RX_FSM_STATE 0x00C1
#define RX_FOM 0x00C2
#define RXDIRECTCTRL2 0x00C7
#define CFGRXOVR4 0x00E9
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v3 03/10] ufs: host: Add common Hibern8 TX FSM polling helper
2026-09-16 8:44 [PATCH v3 00/10] Add S32N79RDB UFS support Larisa Grigore
2026-09-16 8:44 ` [PATCH v3 01/10] ufs: unipro: Move Tx/Rx FSM state definitions to unipro.h Larisa Grigore
2026-09-16 8:44 ` [PATCH v3 02/10] ufs: unipro: Add TX/RX FSM state attributes Larisa Grigore
@ 2026-09-16 8:44 ` Larisa Grigore
2026-09-16 16:22 ` Frank Li
2026-09-16 8:44 ` [PATCH v3 04/10] scsi: ufs: Move Versal2 M-PHY CREG access helpers into ufshcd-dwc Larisa Grigore
` (6 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Larisa Grigore @ 2026-09-16 8:44 UTC (permalink / raw)
To: Larisa Grigore, NXP S32 Linux Team, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa
Cc: linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
Factor out the common logic used to poll TX_FSM_STATE until the TX lanes
enter Hibern8 into ufshcd_check_hibern8().
The HiSilicon and Qualcomm drivers currently implement similar checks
using the UniPro TX_FSM_STATE attribute after link/PHY bring-up. Move
this logic to a common helper in ufshcd so it can be shared across host
controller drivers.
Switch the HiSilicon and Qualcomm drivers to use the new helper and drop
their local implementations. While at it, normalize the "TX lane failed to
reach Hibern8" error path to return -ETIMEDOUT instead of the raw
TX_FSM_STATE value (qcom) or -1 (hisi), so all callers get a proper errno.
This is an intentional, harmless change of the returned error value; the
pass/fail behaviour at the call sites is unchanged.
Unlike the initial implementation, the timeout error is now reported only
once by ufshcd_dme_check_tx_hibern8() after its final check, instead of
per lane.
This also prepares for reusing the same UniPro-specific Hibern8 check in
a subsequent commit.
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
---
drivers/ufs/core/ufshcd.c | 86 +++++++++++++++++++++++++++++++++++++
drivers/ufs/host/ufs-hisi.c | 48 +--------------------
drivers/ufs/host/ufs-qcom.c | 42 +-----------------
include/ufs/ufshcd.h | 3 ++
4 files changed, 91 insertions(+), 88 deletions(-)
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 2ba244cf40ac..f34b7fe54a16 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -4448,6 +4448,92 @@ int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
}
EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
+/**
+ * ufshcd_poll_tx_hibern8_lanes - Check TX_FSM_STATE of all TX lanes once
+ * @hba: host controller instance
+ * @num_lanes: number of TX lanes to check
+ *
+ * Read TX_FSM_STATE for every lane and verify it reached Hibern8.
+ *
+ * Return: 0 if all lanes are in Hibern8, -EAGAIN if any lane is not (yet)
+ * in Hibern8, or a negative errno (e.g. -ETIMEDOUT from a hard UIC command
+ * timeout) if the attribute read fails.
+ */
+static int ufshcd_poll_tx_hibern8_lanes(struct ufs_hba *hba,
+ unsigned int num_lanes)
+{
+ u32 tx_fsm_val = 0;
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < num_lanes; i++) {
+ err = ufshcd_dme_get(hba,
+ UIC_ARG_MIB_SEL(TX_FSM_STATE,
+ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
+ &tx_fsm_val);
+ if (err) {
+ dev_err(hba->dev,
+ "%s: unable to get TX_FSM_STATE for lane %u, err %d\n",
+ __func__, i, err);
+ return err;
+ }
+
+ if (tx_fsm_val != TX_STATE_HIBERN8)
+ return -EAGAIN;
+ }
+
+ return 0;
+}
+
+/**
+ * ufshcd_dme_check_tx_hibern8 - Check if all TX lanes entered Hibern8 state
+ * @hba: host controller instance
+ * @num_lanes: number of TX lanes to check
+ * @timeout_ms: timeout in milliseconds for all lanes
+ *
+ * Return: 0 on success, negative errno on failure.
+ */
+int ufshcd_dme_check_tx_hibern8(struct ufs_hba *hba, unsigned int num_lanes,
+ unsigned int timeout_ms)
+{
+ unsigned long timeout;
+ int err;
+
+ if (!num_lanes)
+ return -EINVAL;
+
+ timeout = jiffies + msecs_to_jiffies(timeout_ms);
+
+ do {
+ err = ufshcd_poll_tx_hibern8_lanes(hba, num_lanes);
+ /*
+ * -EAGAIN means the lanes are simply not in HIBERN8 yet, so
+ * keep polling. Any other error is a real failure and must
+ * be returned immediately instead of being retried.
+ */
+ if (err != -EAGAIN)
+ return err;
+
+ /* sleep for max. 200us */
+ usleep_range(100, 200);
+ } while (time_before(jiffies, timeout));
+
+ /*
+ * We might have been scheduled out for long during polling, so do
+ * one final check before reporting timeout.
+ */
+ err = ufshcd_poll_tx_hibern8_lanes(hba, num_lanes);
+ if (err == -EAGAIN) {
+ dev_err(hba->dev,
+ "%s: timeout waiting for TX lanes to enter HIBERN8\n",
+ __func__);
+ err = -ETIMEDOUT;
+ }
+
+ return err;
+}
+EXPORT_SYMBOL_GPL(ufshcd_dme_check_tx_hibern8);
+
/**
* ufshcd_dme_rmw - get modify set a DME attribute
* @hba: per adapter instance
diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
index bd223bda1ce2..b84075dfe00d 100644
--- a/drivers/ufs/host/ufs-hisi.c
+++ b/drivers/ufs/host/ufs-hisi.c
@@ -22,50 +22,6 @@
#include <ufs/ufshci.h>
#include <ufs/ufs_quirks.h>
-static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
-{
- int err = 0;
- u32 tx_fsm_val_0 = 0;
- u32 tx_fsm_val_1 = 0;
- unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
-
- do {
- err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(TX_FSM_STATE, 0),
- &tx_fsm_val_0);
- err |= ufshcd_dme_get(hba,
- UIC_ARG_MIB_SEL(TX_FSM_STATE, 1), &tx_fsm_val_1);
- if (err || (tx_fsm_val_0 == TX_STATE_HIBERN8 &&
- tx_fsm_val_1 == TX_STATE_HIBERN8))
- break;
-
- /* sleep for max. 200us */
- usleep_range(100, 200);
- } while (time_before(jiffies, timeout));
-
- /*
- * we might have scheduled out for long during polling so
- * check the state again.
- */
- if (time_after(jiffies, timeout)) {
- err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(TX_FSM_STATE, 0),
- &tx_fsm_val_0);
- err |= ufshcd_dme_get(hba,
- UIC_ARG_MIB_SEL(TX_FSM_STATE, 1), &tx_fsm_val_1);
- }
-
- if (err) {
- dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
- __func__, err);
- } else if (tx_fsm_val_0 != TX_STATE_HIBERN8 ||
- tx_fsm_val_1 != TX_STATE_HIBERN8) {
- err = -1;
- dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n",
- __func__, tx_fsm_val_0, tx_fsm_val_1);
- }
-
- return err;
-}
-
static void ufs_hisi_clk_init(struct ufs_hba *hba)
{
struct ufs_hisi_host *host = ufshcd_get_variant(hba);
@@ -224,9 +180,7 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
/* Unipro VS_mphy_disable */
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0);
- err = ufs_hisi_check_hibern8(hba);
- if (err)
- dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
+ err = ufshcd_dme_check_tx_hibern8(hba, 2, HBRN8_POLL_TOUT_MS);
if (!(host->caps & UFS_HISI_CAP_PHY10nm))
ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 1e492dac8d93..815ca82a0878 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -382,46 +382,6 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
return 0;
}
-static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
-{
- int err;
- u32 tx_fsm_val;
- unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
-
- do {
- err = ufshcd_dme_get(hba,
- UIC_ARG_MIB_SEL(TX_FSM_STATE,
- UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
- &tx_fsm_val);
- if (err || tx_fsm_val == TX_STATE_HIBERN8)
- break;
-
- /* sleep for max. 200us */
- usleep_range(100, 200);
- } while (time_before(jiffies, timeout));
-
- /*
- * we might have scheduled out for long during polling so
- * check the state again.
- */
- if (time_after(jiffies, timeout))
- err = ufshcd_dme_get(hba,
- UIC_ARG_MIB_SEL(TX_FSM_STATE,
- UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
- &tx_fsm_val);
-
- if (err) {
- dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
- __func__, err);
- } else if (tx_fsm_val != TX_STATE_HIBERN8) {
- err = tx_fsm_val;
- dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
- __func__, err);
- }
-
- return err;
-}
-
static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
{
ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
@@ -607,7 +567,7 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
break;
case POST_CHANGE:
/* check if UFS PHY moved from DISABLED to HIBERN8 */
- err = ufs_qcom_check_hibern8(hba);
+ err = ufshcd_dme_check_tx_hibern8(hba, 1, HBRN8_POLL_TOUT_MS);
ufs_qcom_enable_hw_clk_gating(hba);
ufs_qcom_ice_enable(host);
ufs_qcom_config_ice_allocator(host);
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index dfd302f2dc7c..0d9d0a26eb20 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -1556,6 +1556,9 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
u8 attr_set, u32 mib_val, u8 peer);
extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
u32 *mib_val, u8 peer);
+extern int ufshcd_dme_check_tx_hibern8(struct ufs_hba *hba,
+ unsigned int num_lanes,
+ unsigned int timeout_ms);
extern int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode,
enum ufshcd_pmc_policy pmc_policy);
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 03/10] ufs: host: Add common Hibern8 TX FSM polling helper
2026-09-16 8:44 ` [PATCH v3 03/10] ufs: host: Add common Hibern8 TX FSM polling helper Larisa Grigore
@ 2026-09-16 16:22 ` Frank Li
2026-09-17 9:00 ` Larisa Ileana Grigore
0 siblings, 1 reply; 17+ messages in thread
From: Frank Li @ 2026-09-16 16:22 UTC (permalink / raw)
To: Larisa Grigore
Cc: NXP S32 Linux Team, Alim Akhtar, Avri Altman, Bart Van Assche,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa ,
linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
On Wed, Sep 16, 2026 at 10:44:04AM +0200, Larisa Grigore wrote:
> Factor out the common logic used to poll TX_FSM_STATE until the TX lanes
> enter Hibern8 into ufshcd_check_hibern8().
>
> The HiSilicon and Qualcomm drivers currently implement similar checks
> using the UniPro TX_FSM_STATE attribute after link/PHY bring-up. Move
> this logic to a common helper in ufshcd so it can be shared across host
> controller drivers.
>
> Switch the HiSilicon and Qualcomm drivers to use the new helper and drop
> their local implementations. While at it, normalize the "TX lane failed to
> reach Hibern8" error path to return -ETIMEDOUT instead of the raw
> TX_FSM_STATE value (qcom) or -1 (hisi), so all callers get a proper errno.
> This is an intentional, harmless change of the returned error value; the
> pass/fail behaviour at the call sites is unchanged.
>
> Unlike the initial implementation, the timeout error is now reported only
> once by ufshcd_dme_check_tx_hibern8() after its final check, instead of
> per lane.
>
> This also prepares for reusing the same UniPro-specific Hibern8 check in
> a subsequent commit.
>
> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
> ---
> drivers/ufs/core/ufshcd.c | 86 +++++++++++++++++++++++++++++++++++++
> drivers/ufs/host/ufs-hisi.c | 48 +--------------------
> drivers/ufs/host/ufs-qcom.c | 42 +-----------------
> include/ufs/ufshcd.h | 3 ++
> 4 files changed, 91 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
> index 2ba244cf40ac..f34b7fe54a16 100644
> --- a/drivers/ufs/core/ufshcd.c
> +++ b/drivers/ufs/core/ufshcd.c
> @@ -4448,6 +4448,92 @@ int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
> }
> EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
>
> +/**
> + * ufshcd_poll_tx_hibern8_lanes - Check TX_FSM_STATE of all TX lanes once
> + * @hba: host controller instance
> + * @num_lanes: number of TX lanes to check
> + *
> + * Read TX_FSM_STATE for every lane and verify it reached Hibern8.
> + *
> + * Return: 0 if all lanes are in Hibern8, -EAGAIN if any lane is not (yet)
> + * in Hibern8, or a negative errno (e.g. -ETIMEDOUT from a hard UIC command
> + * timeout) if the attribute read fails.
> + */
> +static int ufshcd_poll_tx_hibern8_lanes(struct ufs_hba *hba,
> + unsigned int num_lanes)
> +{
> + u32 tx_fsm_val = 0;
> + unsigned int i;
> + int err;
> +
> + for (i = 0; i < num_lanes; i++) {
> + err = ufshcd_dme_get(hba,
> + UIC_ARG_MIB_SEL(TX_FSM_STATE,
> + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
> + &tx_fsm_val);
> + if (err) {
> + dev_err(hba->dev,
> + "%s: unable to get TX_FSM_STATE for lane %u, err %d\n",
> + __func__, i, err);
> + return err;
> + }
> +
> + if (tx_fsm_val != TX_STATE_HIBERN8)
> + return -EAGAIN;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * ufshcd_dme_check_tx_hibern8 - Check if all TX lanes entered Hibern8 state
> + * @hba: host controller instance
> + * @num_lanes: number of TX lanes to check
> + * @timeout_ms: timeout in milliseconds for all lanes
> + *
> + * Return: 0 on success, negative errno on failure.
> + */
> +int ufshcd_dme_check_tx_hibern8(struct ufs_hba *hba, unsigned int num_lanes,
> + unsigned int timeout_ms)
> +{
> + unsigned long timeout;
> + int err;
> +
> + if (!num_lanes)
> + return -EINVAL;
> +
> + timeout = jiffies + msecs_to_jiffies(timeout_ms);
> +
> + do {
> + err = ufshcd_poll_tx_hibern8_lanes(hba, num_lanes);
> + /*
> + * -EAGAIN means the lanes are simply not in HIBERN8 yet, so
> + * keep polling. Any other error is a real failure and must
> + * be returned immediately instead of being retried.
> + */
> + if (err != -EAGAIN)
> + return err;
> +
> + /* sleep for max. 200us */
> + usleep_range(100, 200);
> + } while (time_before(jiffies, timeout));
> +
> + /*
> + * We might have been scheduled out for long during polling, so do
> + * one final check before reporting timeout.
> + */
> + err = ufshcd_poll_tx_hibern8_lanes(hba, num_lanes);
> + if (err == -EAGAIN) {
> + dev_err(hba->dev,
> + "%s: timeout waiting for TX lanes to enter HIBERN8\n",
> + __func__);
> + err = -ETIMEDOUT;
> + }
why not use read read_poll_timeout()
read_poll_timeout(ufshcd_poll_tx_hibern8_lanes, err, err != -EAGAIN, timeout_ms,
0, hba, numlanes);
Frank
> +
> + return err;
> +}
> +EXPORT_SYMBOL_GPL(ufshcd_dme_check_tx_hibern8);
> +
> /**
> * ufshcd_dme_rmw - get modify set a DME attribute
> * @hba: per adapter instance
> diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
> index bd223bda1ce2..b84075dfe00d 100644
> --- a/drivers/ufs/host/ufs-hisi.c
> +++ b/drivers/ufs/host/ufs-hisi.c
> @@ -22,50 +22,6 @@
> #include <ufs/ufshci.h>
> #include <ufs/ufs_quirks.h>
>
> -static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
> -{
> - int err = 0;
> - u32 tx_fsm_val_0 = 0;
> - u32 tx_fsm_val_1 = 0;
> - unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
> -
> - do {
> - err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(TX_FSM_STATE, 0),
> - &tx_fsm_val_0);
> - err |= ufshcd_dme_get(hba,
> - UIC_ARG_MIB_SEL(TX_FSM_STATE, 1), &tx_fsm_val_1);
> - if (err || (tx_fsm_val_0 == TX_STATE_HIBERN8 &&
> - tx_fsm_val_1 == TX_STATE_HIBERN8))
> - break;
> -
> - /* sleep for max. 200us */
> - usleep_range(100, 200);
> - } while (time_before(jiffies, timeout));
> -
> - /*
> - * we might have scheduled out for long during polling so
> - * check the state again.
> - */
> - if (time_after(jiffies, timeout)) {
> - err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(TX_FSM_STATE, 0),
> - &tx_fsm_val_0);
> - err |= ufshcd_dme_get(hba,
> - UIC_ARG_MIB_SEL(TX_FSM_STATE, 1), &tx_fsm_val_1);
> - }
> -
> - if (err) {
> - dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
> - __func__, err);
> - } else if (tx_fsm_val_0 != TX_STATE_HIBERN8 ||
> - tx_fsm_val_1 != TX_STATE_HIBERN8) {
> - err = -1;
> - dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n",
> - __func__, tx_fsm_val_0, tx_fsm_val_1);
> - }
> -
> - return err;
> -}
> -
> static void ufs_hisi_clk_init(struct ufs_hba *hba)
> {
> struct ufs_hisi_host *host = ufshcd_get_variant(hba);
> @@ -224,9 +180,7 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
>
> /* Unipro VS_mphy_disable */
> ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0);
> - err = ufs_hisi_check_hibern8(hba);
> - if (err)
> - dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
> + err = ufshcd_dme_check_tx_hibern8(hba, 2, HBRN8_POLL_TOUT_MS);
>
> if (!(host->caps & UFS_HISI_CAP_PHY10nm))
> ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 1e492dac8d93..815ca82a0878 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -382,46 +382,6 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
> return 0;
> }
>
> -static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
> -{
> - int err;
> - u32 tx_fsm_val;
> - unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
> -
> - do {
> - err = ufshcd_dme_get(hba,
> - UIC_ARG_MIB_SEL(TX_FSM_STATE,
> - UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
> - &tx_fsm_val);
> - if (err || tx_fsm_val == TX_STATE_HIBERN8)
> - break;
> -
> - /* sleep for max. 200us */
> - usleep_range(100, 200);
> - } while (time_before(jiffies, timeout));
> -
> - /*
> - * we might have scheduled out for long during polling so
> - * check the state again.
> - */
> - if (time_after(jiffies, timeout))
> - err = ufshcd_dme_get(hba,
> - UIC_ARG_MIB_SEL(TX_FSM_STATE,
> - UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
> - &tx_fsm_val);
> -
> - if (err) {
> - dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
> - __func__, err);
> - } else if (tx_fsm_val != TX_STATE_HIBERN8) {
> - err = tx_fsm_val;
> - dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
> - __func__, err);
> - }
> -
> - return err;
> -}
> -
> static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
> {
> ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
> @@ -607,7 +567,7 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
> break;
> case POST_CHANGE:
> /* check if UFS PHY moved from DISABLED to HIBERN8 */
> - err = ufs_qcom_check_hibern8(hba);
> + err = ufshcd_dme_check_tx_hibern8(hba, 1, HBRN8_POLL_TOUT_MS);
> ufs_qcom_enable_hw_clk_gating(hba);
> ufs_qcom_ice_enable(host);
> ufs_qcom_config_ice_allocator(host);
> diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
> index dfd302f2dc7c..0d9d0a26eb20 100644
> --- a/include/ufs/ufshcd.h
> +++ b/include/ufs/ufshcd.h
> @@ -1556,6 +1556,9 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
> u8 attr_set, u32 mib_val, u8 peer);
> extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
> u32 *mib_val, u8 peer);
> +extern int ufshcd_dme_check_tx_hibern8(struct ufs_hba *hba,
> + unsigned int num_lanes,
> + unsigned int timeout_ms);
> extern int ufshcd_change_power_mode(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *pwr_mode,
> enum ufshcd_pmc_policy pmc_policy);
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 03/10] ufs: host: Add common Hibern8 TX FSM polling helper
2026-09-16 16:22 ` Frank Li
@ 2026-09-17 9:00 ` Larisa Ileana Grigore
0 siblings, 0 replies; 17+ messages in thread
From: Larisa Ileana Grigore @ 2026-09-17 9:00 UTC (permalink / raw)
To: Frank Li
Cc: NXP S32 Linux Team, Alim Akhtar, Avri Altman, Bart Van Assche,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa, linux-scsi,
devicetree, linux-kernel, imx, linux-arm-kernel, linux-arm-msm,
clizzi, aruizrui, eballetb, echanude
On 9/16/2026 7:22 PM, Frank Li wrote:
> On Wed, Sep 16, 2026 at 10:44:04AM +0200, Larisa Grigore wrote:
>> Factor out the common logic used to poll TX_FSM_STATE until the TX lanes
>> enter Hibern8 into ufshcd_check_hibern8().
>>
>> The HiSilicon and Qualcomm drivers currently implement similar checks
>> using the UniPro TX_FSM_STATE attribute after link/PHY bring-up. Move
>> this logic to a common helper in ufshcd so it can be shared across host
>> controller drivers.
>>
>> Switch the HiSilicon and Qualcomm drivers to use the new helper and drop
>> their local implementations. While at it, normalize the "TX lane failed to
>> reach Hibern8" error path to return -ETIMEDOUT instead of the raw
>> TX_FSM_STATE value (qcom) or -1 (hisi), so all callers get a proper errno.
>> This is an intentional, harmless change of the returned error value; the
>> pass/fail behaviour at the call sites is unchanged.
>>
>> Unlike the initial implementation, the timeout error is now reported only
>> once by ufshcd_dme_check_tx_hibern8() after its final check, instead of
>> per lane.
>>
>> This also prepares for reusing the same UniPro-specific Hibern8 check in
>> a subsequent commit.
>>
>> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
>> ---
>> drivers/ufs/core/ufshcd.c | 86 +++++++++++++++++++++++++++++++++++++
>> drivers/ufs/host/ufs-hisi.c | 48 +--------------------
>> drivers/ufs/host/ufs-qcom.c | 42 +-----------------
>> include/ufs/ufshcd.h | 3 ++
>> 4 files changed, 91 insertions(+), 88 deletions(-)
>>
>> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
>> index 2ba244cf40ac..f34b7fe54a16 100644
>> --- a/drivers/ufs/core/ufshcd.c
>> +++ b/drivers/ufs/core/ufshcd.c
>> @@ -4448,6 +4448,92 @@ int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
>> }
>> EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
>>
>> +/**
>> + * ufshcd_poll_tx_hibern8_lanes - Check TX_FSM_STATE of all TX lanes once
>> + * @hba: host controller instance
>> + * @num_lanes: number of TX lanes to check
>> + *
>> + * Read TX_FSM_STATE for every lane and verify it reached Hibern8.
>> + *
>> + * Return: 0 if all lanes are in Hibern8, -EAGAIN if any lane is not (yet)
>> + * in Hibern8, or a negative errno (e.g. -ETIMEDOUT from a hard UIC command
>> + * timeout) if the attribute read fails.
>> + */
>> +static int ufshcd_poll_tx_hibern8_lanes(struct ufs_hba *hba,
>> + unsigned int num_lanes)
>> +{
>> + u32 tx_fsm_val = 0;
>> + unsigned int i;
>> + int err;
>> +
>> + for (i = 0; i < num_lanes; i++) {
>> + err = ufshcd_dme_get(hba,
>> + UIC_ARG_MIB_SEL(TX_FSM_STATE,
>> + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
>> + &tx_fsm_val);
>> + if (err) {
>> + dev_err(hba->dev,
>> + "%s: unable to get TX_FSM_STATE for lane %u, err %d\n",
>> + __func__, i, err);
>> + return err;
>> + }
>> +
>> + if (tx_fsm_val != TX_STATE_HIBERN8)
>> + return -EAGAIN;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +/**
>> + * ufshcd_dme_check_tx_hibern8 - Check if all TX lanes entered Hibern8 state
>> + * @hba: host controller instance
>> + * @num_lanes: number of TX lanes to check
>> + * @timeout_ms: timeout in milliseconds for all lanes
>> + *
>> + * Return: 0 on success, negative errno on failure.
>> + */
>> +int ufshcd_dme_check_tx_hibern8(struct ufs_hba *hba, unsigned int num_lanes,
>> + unsigned int timeout_ms)
>> +{
>> + unsigned long timeout;
>> + int err;
>> +
>> + if (!num_lanes)
>> + return -EINVAL;
>> +
>> + timeout = jiffies + msecs_to_jiffies(timeout_ms);
>> +
>> + do {
>> + err = ufshcd_poll_tx_hibern8_lanes(hba, num_lanes);
>> + /*
>> + * -EAGAIN means the lanes are simply not in HIBERN8 yet, so
>> + * keep polling. Any other error is a real failure and must
>> + * be returned immediately instead of being retried.
>> + */
>> + if (err != -EAGAIN)
>> + return err;
>> +
>> + /* sleep for max. 200us */
>> + usleep_range(100, 200);
>> + } while (time_before(jiffies, timeout));
>> +
>> + /*
>> + * We might have been scheduled out for long during polling, so do
>> + * one final check before reporting timeout.
>> + */
>> + err = ufshcd_poll_tx_hibern8_lanes(hba, num_lanes);
>> + if (err == -EAGAIN) {
>> + dev_err(hba->dev,
>> + "%s: timeout waiting for TX lanes to enter HIBERN8\n",
>> + __func__);
>> + err = -ETIMEDOUT;
>> + }
>
>
> why not use read read_poll_timeout()
>
> read_poll_timeout(ufshcd_poll_tx_hibern8_lanes, err, err != -EAGAIN, timeout_ms,
> 0, hba, numlanes);
>
>
> Frank
>
Thank you for the suggestion!
Best regards,
Larisa
>> +
>> + return err;
>> +}
>> +EXPORT_SYMBOL_GPL(ufshcd_dme_check_tx_hibern8);
>> +
>> /**
>> * ufshcd_dme_rmw - get modify set a DME attribute
>> * @hba: per adapter instance
>> diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
>> index bd223bda1ce2..b84075dfe00d 100644
>> --- a/drivers/ufs/host/ufs-hisi.c
>> +++ b/drivers/ufs/host/ufs-hisi.c
>> @@ -22,50 +22,6 @@
>> #include <ufs/ufshci.h>
>> #include <ufs/ufs_quirks.h>
>>
>> -static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
>> -{
>> - int err = 0;
>> - u32 tx_fsm_val_0 = 0;
>> - u32 tx_fsm_val_1 = 0;
>> - unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
>> -
>> - do {
>> - err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(TX_FSM_STATE, 0),
>> - &tx_fsm_val_0);
>> - err |= ufshcd_dme_get(hba,
>> - UIC_ARG_MIB_SEL(TX_FSM_STATE, 1), &tx_fsm_val_1);
>> - if (err || (tx_fsm_val_0 == TX_STATE_HIBERN8 &&
>> - tx_fsm_val_1 == TX_STATE_HIBERN8))
>> - break;
>> -
>> - /* sleep for max. 200us */
>> - usleep_range(100, 200);
>> - } while (time_before(jiffies, timeout));
>> -
>> - /*
>> - * we might have scheduled out for long during polling so
>> - * check the state again.
>> - */
>> - if (time_after(jiffies, timeout)) {
>> - err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(TX_FSM_STATE, 0),
>> - &tx_fsm_val_0);
>> - err |= ufshcd_dme_get(hba,
>> - UIC_ARG_MIB_SEL(TX_FSM_STATE, 1), &tx_fsm_val_1);
>> - }
>> -
>> - if (err) {
>> - dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
>> - __func__, err);
>> - } else if (tx_fsm_val_0 != TX_STATE_HIBERN8 ||
>> - tx_fsm_val_1 != TX_STATE_HIBERN8) {
>> - err = -1;
>> - dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n",
>> - __func__, tx_fsm_val_0, tx_fsm_val_1);
>> - }
>> -
>> - return err;
>> -}
>> -
>> static void ufs_hisi_clk_init(struct ufs_hba *hba)
>> {
>> struct ufs_hisi_host *host = ufshcd_get_variant(hba);
>> @@ -224,9 +180,7 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
>>
>> /* Unipro VS_mphy_disable */
>> ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0);
>> - err = ufs_hisi_check_hibern8(hba);
>> - if (err)
>> - dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
>> + err = ufshcd_dme_check_tx_hibern8(hba, 2, HBRN8_POLL_TOUT_MS);
>>
>> if (!(host->caps & UFS_HISI_CAP_PHY10nm))
>> ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index 1e492dac8d93..815ca82a0878 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -382,46 +382,6 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
>> return 0;
>> }
>>
>> -static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
>> -{
>> - int err;
>> - u32 tx_fsm_val;
>> - unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
>> -
>> - do {
>> - err = ufshcd_dme_get(hba,
>> - UIC_ARG_MIB_SEL(TX_FSM_STATE,
>> - UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
>> - &tx_fsm_val);
>> - if (err || tx_fsm_val == TX_STATE_HIBERN8)
>> - break;
>> -
>> - /* sleep for max. 200us */
>> - usleep_range(100, 200);
>> - } while (time_before(jiffies, timeout));
>> -
>> - /*
>> - * we might have scheduled out for long during polling so
>> - * check the state again.
>> - */
>> - if (time_after(jiffies, timeout))
>> - err = ufshcd_dme_get(hba,
>> - UIC_ARG_MIB_SEL(TX_FSM_STATE,
>> - UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
>> - &tx_fsm_val);
>> -
>> - if (err) {
>> - dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
>> - __func__, err);
>> - } else if (tx_fsm_val != TX_STATE_HIBERN8) {
>> - err = tx_fsm_val;
>> - dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
>> - __func__, err);
>> - }
>> -
>> - return err;
>> -}
>> -
>> static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
>> {
>> ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
>> @@ -607,7 +567,7 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
>> break;
>> case POST_CHANGE:
>> /* check if UFS PHY moved from DISABLED to HIBERN8 */
>> - err = ufs_qcom_check_hibern8(hba);
>> + err = ufshcd_dme_check_tx_hibern8(hba, 1, HBRN8_POLL_TOUT_MS);
>> ufs_qcom_enable_hw_clk_gating(hba);
>> ufs_qcom_ice_enable(host);
>> ufs_qcom_config_ice_allocator(host);
>> diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
>> index dfd302f2dc7c..0d9d0a26eb20 100644
>> --- a/include/ufs/ufshcd.h
>> +++ b/include/ufs/ufshcd.h
>> @@ -1556,6 +1556,9 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
>> u8 attr_set, u32 mib_val, u8 peer);
>> extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
>> u32 *mib_val, u8 peer);
>> +extern int ufshcd_dme_check_tx_hibern8(struct ufs_hba *hba,
>> + unsigned int num_lanes,
>> + unsigned int timeout_ms);
>> extern int ufshcd_change_power_mode(struct ufs_hba *hba,
>> struct ufs_pa_layer_attr *pwr_mode,
>> enum ufshcd_pmc_policy pmc_policy);
>> --
>> 2.43.0
>>
>>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 04/10] scsi: ufs: Move Versal2 M-PHY CREG access helpers into ufshcd-dwc
2026-09-16 8:44 [PATCH v3 00/10] Add S32N79RDB UFS support Larisa Grigore
` (2 preceding siblings ...)
2026-09-16 8:44 ` [PATCH v3 03/10] ufs: host: Add common Hibern8 TX FSM polling helper Larisa Grigore
@ 2026-09-16 8:44 ` Larisa Grigore
2026-09-16 16:29 ` Frank Li
2026-09-16 8:44 ` [PATCH v3 05/10] scsi: ufs: dwc: Export common clock divider and link status helpers Larisa Grigore
` (5 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Larisa Grigore @ 2026-09-16 8:44 UTC (permalink / raw)
To: Larisa Grigore, NXP S32 Linux Team, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa
Cc: linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
The AMD Versal Gen 2 UFS platform driver carries local helpers to access
M-PHY control registers through the UniPro CREG interface.
Move these helpers into the common Synopsys DWC layer as
ufshcd_dwc_phy_reg_read() and ufshcd_dwc_phy_reg_write(). This avoids code
duplication in DWC-based glue drivers and provides a single implementation
for future reuse.
Dropped `static` from `phy_write_attrs` and `phy_read_attrs` since there
is no benefit in keeping them persistent.
Update the AMD Versal2 glue driver to use the new ufshcd-dwc helpers.
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
---
drivers/ufs/host/ufs-amd-versal2.c | 85 ++++++------------------------
drivers/ufs/host/ufshcd-dwc.c | 69 ++++++++++++++++++++++++
drivers/ufs/host/ufshcd-dwc.h | 2 +
3 files changed, 88 insertions(+), 68 deletions(-)
diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c
index 0d4d5e98ad65..c7da95999c85 100644
--- a/drivers/ufs/host/ufs-amd-versal2.c
+++ b/drivers/ufs/host/ufs-amd-versal2.c
@@ -43,57 +43,6 @@ struct ufs_versal2_host {
u8 ctlecompval1;
};
-static int ufs_versal2_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val)
-{
- static struct ufshcd_dme_attr_val phy_write_attrs[] = {
- { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL },
- { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL },
- { UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL },
- { UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL },
- { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL },
- { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL }
- };
-
- phy_write_attrs[0].mib_val = (u8)addr;
- phy_write_attrs[1].mib_val = (u8)(addr >> 8);
- phy_write_attrs[2].mib_val = (u8)val;
- phy_write_attrs[3].mib_val = (u8)(val >> 8);
-
- return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_write_attrs));
-}
-
-static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val)
-{
- u32 mib_val;
- int ret;
- static struct ufshcd_dme_attr_val phy_read_attrs[] = {
- { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL },
- { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL },
- { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL },
- { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL }
- };
-
- phy_read_attrs[0].mib_val = (u8)addr;
- phy_read_attrs[1].mib_val = (u8)(addr >> 8);
-
- ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read_attrs));
- if (ret)
- return ret;
-
- ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val);
- if (ret)
- return ret;
-
- *val = mib_val;
- ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val);
- if (ret)
- return ret;
-
- *val |= (mib_val << 8);
-
- return 0;
-}
-
static int ufs_versal2_enable_phy(struct ufs_hba *hba)
{
u32 offset, reg;
@@ -162,64 +111,64 @@ static int ufs_versal2_setup_phy(struct ufs_hba *hba)
u32 reg;
/* Bypass RX-AFE offset calibrations (ATT/CTLE) */
- ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(0), ®);
+ ret = ufshcd_dwc_phy_reg_read(hba, FAST_FLAGS(0), ®);
if (ret)
return ret;
reg |= MPHY_FAST_RX_AFE_CAL;
- ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(0), reg);
+ ret = ufshcd_dwc_phy_reg_write(hba, FAST_FLAGS(0), reg);
if (ret)
return ret;
- ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(1), ®);
+ ret = ufshcd_dwc_phy_reg_read(hba, FAST_FLAGS(1), ®);
if (ret)
return ret;
reg |= MPHY_FAST_RX_AFE_CAL;
- ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(1), reg);
+ ret = ufshcd_dwc_phy_reg_write(hba, FAST_FLAGS(1), reg);
if (ret)
return ret;
/* Program ATT and CTLE compensation values */
if (host->attcompval0) {
- ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0);
+ ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0);
if (ret)
return ret;
}
if (host->attcompval1) {
- ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1);
+ ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1);
if (ret)
return ret;
}
if (host->ctlecompval0) {
- ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0);
+ ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0);
if (ret)
return ret;
}
if (host->ctlecompval1) {
- ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1);
+ ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1);
if (ret)
return ret;
}
- ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(0), ®);
+ ret = ufshcd_dwc_phy_reg_read(hba, FW_CALIB_CCFG(0), ®);
if (ret)
return ret;
reg |= MPHY_FW_CALIB_CFG_VAL;
- ret = ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(0), reg);
+ ret = ufshcd_dwc_phy_reg_write(hba, FW_CALIB_CCFG(0), reg);
if (ret)
return ret;
- ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(1), ®);
+ ret = ufshcd_dwc_phy_reg_read(hba, FW_CALIB_CCFG(1), ®);
if (ret)
return ret;
reg |= MPHY_FW_CALIB_CFG_VAL;
- return ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(1), reg);
+ return ufshcd_dwc_phy_reg_write(hba, FW_CALIB_CCFG(1), reg);
}
static int ufs_versal2_phy_init(struct ufs_hba *hba)
@@ -406,7 +355,7 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_
for (lane = 0; lane < activelanes; lane++) {
time_left = TIMEOUT_MICROSEC;
- ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®);
+ ret = ufshcd_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®);
if (ret)
return ret;
@@ -416,12 +365,12 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_
else
reg &= ~MPHY_RX_OVRD_VAL;
- ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg);
+ ret = ufshcd_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg);
if (ret)
return ret;
do {
- ret = ufs_versal2_phy_reg_read(hba, RX_PCS_OUT(lane), ®);
+ ret = ufshcd_dwc_phy_reg_read(hba, RX_PCS_OUT(lane), ®);
if (ret)
return ret;
@@ -483,12 +432,12 @@ static int ufs_versal2_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_ch
/* Remove rx_req override */
for (lane = 0; lane < dev_req_params->lane_tx; lane++) {
- ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®);
+ ret = ufshcd_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®);
if (ret)
return ret;
reg &= ~MPHY_RX_OVRD_EN;
- ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg);
+ ret = ufshcd_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg);
if (ret)
return ret;
}
diff --git a/drivers/ufs/host/ufshcd-dwc.c b/drivers/ufs/host/ufshcd-dwc.c
index 21b1cf912dcc..0eceec543d14 100644
--- a/drivers/ufs/host/ufshcd-dwc.c
+++ b/drivers/ufs/host/ufshcd-dwc.c
@@ -141,6 +141,75 @@ int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
}
EXPORT_SYMBOL(ufshcd_dwc_link_startup_notify);
+/**
+ * ufshcd_dwc_phy_reg_write - Write a DWC M-PHY CREG register
+ * @hba: private structure pointer
+ * @addr: M-PHY CREG register address
+ * @val: value to write
+ *
+ * Write a 16-bit M-PHY CREG register through the Synopsys DesignWare
+ * UniPro indirect register access interface.
+ *
+ * Return: 0 on success, non-zero value on failure.
+ */
+int ufshcd_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val)
+{
+ const struct ufshcd_dme_attr_val phy_write_attrs[] = {
+ { UIC_ARG_MIB(CBCREGADDRLSB), (u8)addr, DME_LOCAL },
+ { UIC_ARG_MIB(CBCREGADDRMSB), (u8)(addr >> 8), DME_LOCAL },
+ { UIC_ARG_MIB(CBCREGWRLSB), (u8)val, DME_LOCAL },
+ { UIC_ARG_MIB(CBCREGWRMSB), (u8)(val >> 8), DME_LOCAL },
+ { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL },
+ { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL }
+ };
+
+ return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs,
+ ARRAY_SIZE(phy_write_attrs));
+}
+EXPORT_SYMBOL(ufshcd_dwc_phy_reg_write);
+
+/**
+ * ufshcd_dwc_phy_reg_read - Read a DWC M-PHY CREG register
+ * @hba: private structure pointer
+ * @addr: M-PHY CREG register address
+ * @val: pointer where the read value is stored
+ *
+ * Read a 16-bit M-PHY CREG register through the Synopsys DesignWare
+ * UniPro indirect register access interface.
+ *
+ * Return: 0 on success, non-zero value on failure.
+ */
+int ufshcd_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val)
+{
+ const struct ufshcd_dme_attr_val phy_read_attrs[] = {
+ { UIC_ARG_MIB(CBCREGADDRLSB), (u8)addr, DME_LOCAL },
+ { UIC_ARG_MIB(CBCREGADDRMSB), (u8)(addr >> 8), DME_LOCAL },
+ { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL },
+ { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL }
+ };
+ u32 mib_val;
+ int ret;
+
+ ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs,
+ ARRAY_SIZE(phy_read_attrs));
+ if (ret)
+ return ret;
+
+ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val);
+ if (ret)
+ return ret;
+
+ *val = mib_val;
+ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val);
+ if (ret)
+ return ret;
+
+ *val |= (mib_val << 8);
+
+ return 0;
+}
+EXPORT_SYMBOL(ufshcd_dwc_phy_reg_read);
+
MODULE_AUTHOR("Joao Pinto <Joao.Pinto@synopsys.com>");
MODULE_DESCRIPTION("UFS Host driver for Synopsys Designware Core");
MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h
index 0406f2bb576b..d8673cd54d4c 100644
--- a/drivers/ufs/host/ufshcd-dwc.h
+++ b/drivers/ufs/host/ufshcd-dwc.h
@@ -45,4 +45,6 @@ int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
enum ufs_notify_change_status status);
int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
const struct ufshcd_dme_attr_val *v, int n);
+int ufshcd_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val);
+int ufshcd_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val);
#endif /* End of Header */
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 04/10] scsi: ufs: Move Versal2 M-PHY CREG access helpers into ufshcd-dwc
2026-09-16 8:44 ` [PATCH v3 04/10] scsi: ufs: Move Versal2 M-PHY CREG access helpers into ufshcd-dwc Larisa Grigore
@ 2026-09-16 16:29 ` Frank Li
0 siblings, 0 replies; 17+ messages in thread
From: Frank Li @ 2026-09-16 16:29 UTC (permalink / raw)
To: Larisa Grigore
Cc: NXP S32 Linux Team, Alim Akhtar, Avri Altman, Bart Van Assche,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa ,
linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
On Wed, Sep 16, 2026 at 10:44:05AM +0200, Larisa Grigore wrote:
> The AMD Versal Gen 2 UFS platform driver carries local helpers to access
> M-PHY control registers through the UniPro CREG interface.
>
> Move these helpers into the common Synopsys DWC layer as
> ufshcd_dwc_phy_reg_read() and ufshcd_dwc_phy_reg_write(). This avoids code
> duplication in DWC-based glue drivers and provides a single implementation
> for future reuse.
Nit: add empty line between paragraph.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Dropped `static` from `phy_write_attrs` and `phy_read_attrs` since there
> is no benefit in keeping them persistent.
>
> Update the AMD Versal2 glue driver to use the new ufshcd-dwc helpers.
>
> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
> ---
> drivers/ufs/host/ufs-amd-versal2.c | 85 ++++++------------------------
> drivers/ufs/host/ufshcd-dwc.c | 69 ++++++++++++++++++++++++
> drivers/ufs/host/ufshcd-dwc.h | 2 +
> 3 files changed, 88 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c
> index 0d4d5e98ad65..c7da95999c85 100644
> --- a/drivers/ufs/host/ufs-amd-versal2.c
> +++ b/drivers/ufs/host/ufs-amd-versal2.c
> @@ -43,57 +43,6 @@ struct ufs_versal2_host {
> u8 ctlecompval1;
> };
>
> -static int ufs_versal2_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val)
> -{
> - static struct ufshcd_dme_attr_val phy_write_attrs[] = {
> - { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL },
> - { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL },
> - { UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL },
> - { UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL },
> - { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL },
> - { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL }
> - };
> -
> - phy_write_attrs[0].mib_val = (u8)addr;
> - phy_write_attrs[1].mib_val = (u8)(addr >> 8);
> - phy_write_attrs[2].mib_val = (u8)val;
> - phy_write_attrs[3].mib_val = (u8)(val >> 8);
> -
> - return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_write_attrs));
> -}
> -
> -static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val)
> -{
> - u32 mib_val;
> - int ret;
> - static struct ufshcd_dme_attr_val phy_read_attrs[] = {
> - { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL },
> - { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL },
> - { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL },
> - { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL }
> - };
> -
> - phy_read_attrs[0].mib_val = (u8)addr;
> - phy_read_attrs[1].mib_val = (u8)(addr >> 8);
> -
> - ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read_attrs));
> - if (ret)
> - return ret;
> -
> - ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val);
> - if (ret)
> - return ret;
> -
> - *val = mib_val;
> - ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val);
> - if (ret)
> - return ret;
> -
> - *val |= (mib_val << 8);
> -
> - return 0;
> -}
> -
> static int ufs_versal2_enable_phy(struct ufs_hba *hba)
> {
> u32 offset, reg;
> @@ -162,64 +111,64 @@ static int ufs_versal2_setup_phy(struct ufs_hba *hba)
> u32 reg;
>
> /* Bypass RX-AFE offset calibrations (ATT/CTLE) */
> - ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(0), ®);
> + ret = ufshcd_dwc_phy_reg_read(hba, FAST_FLAGS(0), ®);
> if (ret)
> return ret;
>
> reg |= MPHY_FAST_RX_AFE_CAL;
> - ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(0), reg);
> + ret = ufshcd_dwc_phy_reg_write(hba, FAST_FLAGS(0), reg);
> if (ret)
> return ret;
>
> - ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(1), ®);
> + ret = ufshcd_dwc_phy_reg_read(hba, FAST_FLAGS(1), ®);
> if (ret)
> return ret;
>
> reg |= MPHY_FAST_RX_AFE_CAL;
> - ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(1), reg);
> + ret = ufshcd_dwc_phy_reg_write(hba, FAST_FLAGS(1), reg);
> if (ret)
> return ret;
>
> /* Program ATT and CTLE compensation values */
> if (host->attcompval0) {
> - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0);
> + ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0);
> if (ret)
> return ret;
> }
>
> if (host->attcompval1) {
> - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1);
> + ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1);
> if (ret)
> return ret;
> }
>
> if (host->ctlecompval0) {
> - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0);
> + ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0);
> if (ret)
> return ret;
> }
>
> if (host->ctlecompval1) {
> - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1);
> + ret = ufshcd_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1);
> if (ret)
> return ret;
> }
>
> - ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(0), ®);
> + ret = ufshcd_dwc_phy_reg_read(hba, FW_CALIB_CCFG(0), ®);
> if (ret)
> return ret;
>
> reg |= MPHY_FW_CALIB_CFG_VAL;
> - ret = ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(0), reg);
> + ret = ufshcd_dwc_phy_reg_write(hba, FW_CALIB_CCFG(0), reg);
> if (ret)
> return ret;
>
> - ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(1), ®);
> + ret = ufshcd_dwc_phy_reg_read(hba, FW_CALIB_CCFG(1), ®);
> if (ret)
> return ret;
>
> reg |= MPHY_FW_CALIB_CFG_VAL;
> - return ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(1), reg);
> + return ufshcd_dwc_phy_reg_write(hba, FW_CALIB_CCFG(1), reg);
> }
>
> static int ufs_versal2_phy_init(struct ufs_hba *hba)
> @@ -406,7 +355,7 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_
>
> for (lane = 0; lane < activelanes; lane++) {
> time_left = TIMEOUT_MICROSEC;
> - ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®);
> + ret = ufshcd_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®);
> if (ret)
> return ret;
>
> @@ -416,12 +365,12 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_
> else
> reg &= ~MPHY_RX_OVRD_VAL;
>
> - ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg);
> + ret = ufshcd_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg);
> if (ret)
> return ret;
>
> do {
> - ret = ufs_versal2_phy_reg_read(hba, RX_PCS_OUT(lane), ®);
> + ret = ufshcd_dwc_phy_reg_read(hba, RX_PCS_OUT(lane), ®);
> if (ret)
> return ret;
>
> @@ -483,12 +432,12 @@ static int ufs_versal2_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_ch
>
> /* Remove rx_req override */
> for (lane = 0; lane < dev_req_params->lane_tx; lane++) {
> - ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®);
> + ret = ufshcd_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®);
> if (ret)
> return ret;
>
> reg &= ~MPHY_RX_OVRD_EN;
> - ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg);
> + ret = ufshcd_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg);
> if (ret)
> return ret;
> }
> diff --git a/drivers/ufs/host/ufshcd-dwc.c b/drivers/ufs/host/ufshcd-dwc.c
> index 21b1cf912dcc..0eceec543d14 100644
> --- a/drivers/ufs/host/ufshcd-dwc.c
> +++ b/drivers/ufs/host/ufshcd-dwc.c
> @@ -141,6 +141,75 @@ int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
> }
> EXPORT_SYMBOL(ufshcd_dwc_link_startup_notify);
>
> +/**
> + * ufshcd_dwc_phy_reg_write - Write a DWC M-PHY CREG register
> + * @hba: private structure pointer
> + * @addr: M-PHY CREG register address
> + * @val: value to write
> + *
> + * Write a 16-bit M-PHY CREG register through the Synopsys DesignWare
> + * UniPro indirect register access interface.
> + *
> + * Return: 0 on success, non-zero value on failure.
> + */
> +int ufshcd_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val)
> +{
> + const struct ufshcd_dme_attr_val phy_write_attrs[] = {
> + { UIC_ARG_MIB(CBCREGADDRLSB), (u8)addr, DME_LOCAL },
> + { UIC_ARG_MIB(CBCREGADDRMSB), (u8)(addr >> 8), DME_LOCAL },
> + { UIC_ARG_MIB(CBCREGWRLSB), (u8)val, DME_LOCAL },
> + { UIC_ARG_MIB(CBCREGWRMSB), (u8)(val >> 8), DME_LOCAL },
> + { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL },
> + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL }
> + };
> +
> + return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs,
> + ARRAY_SIZE(phy_write_attrs));
> +}
> +EXPORT_SYMBOL(ufshcd_dwc_phy_reg_write);
> +
> +/**
> + * ufshcd_dwc_phy_reg_read - Read a DWC M-PHY CREG register
> + * @hba: private structure pointer
> + * @addr: M-PHY CREG register address
> + * @val: pointer where the read value is stored
> + *
> + * Read a 16-bit M-PHY CREG register through the Synopsys DesignWare
> + * UniPro indirect register access interface.
> + *
> + * Return: 0 on success, non-zero value on failure.
> + */
> +int ufshcd_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val)
> +{
> + const struct ufshcd_dme_attr_val phy_read_attrs[] = {
> + { UIC_ARG_MIB(CBCREGADDRLSB), (u8)addr, DME_LOCAL },
> + { UIC_ARG_MIB(CBCREGADDRMSB), (u8)(addr >> 8), DME_LOCAL },
> + { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL },
> + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL }
> + };
> + u32 mib_val;
> + int ret;
> +
> + ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs,
> + ARRAY_SIZE(phy_read_attrs));
> + if (ret)
> + return ret;
> +
> + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val);
> + if (ret)
> + return ret;
> +
> + *val = mib_val;
> + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val);
> + if (ret)
> + return ret;
> +
> + *val |= (mib_val << 8);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(ufshcd_dwc_phy_reg_read);
> +
> MODULE_AUTHOR("Joao Pinto <Joao.Pinto@synopsys.com>");
> MODULE_DESCRIPTION("UFS Host driver for Synopsys Designware Core");
> MODULE_LICENSE("Dual BSD/GPL");
> diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h
> index 0406f2bb576b..d8673cd54d4c 100644
> --- a/drivers/ufs/host/ufshcd-dwc.h
> +++ b/drivers/ufs/host/ufshcd-dwc.h
> @@ -45,4 +45,6 @@ int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
> enum ufs_notify_change_status status);
> int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
> const struct ufshcd_dme_attr_val *v, int n);
> +int ufshcd_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val);
> +int ufshcd_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val);
> #endif /* End of Header */
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 05/10] scsi: ufs: dwc: Export common clock divider and link status helpers
2026-09-16 8:44 [PATCH v3 00/10] Add S32N79RDB UFS support Larisa Grigore
` (3 preceding siblings ...)
2026-09-16 8:44 ` [PATCH v3 04/10] scsi: ufs: Move Versal2 M-PHY CREG access helpers into ufshcd-dwc Larisa Grigore
@ 2026-09-16 8:44 ` Larisa Grigore
2026-09-16 8:44 ` [PATCH v3 06/10] dt-bindings: ufs: Add NXP S32N79 UFS host controller Larisa Grigore
` (4 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Larisa Grigore @ 2026-09-16 8:44 UTC (permalink / raw)
To: Larisa Grigore, NXP S32 Linux Team, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa
Cc: linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
Make ufshcd_dwc_program_clk_div() and ufshcd_dwc_link_is_up() available to
DWC-based platform glue drivers. These helpers are needed by platform
drivers that must program the controller HCLK divider and verify link state
during their vendor-specific initialization flows.
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
drivers/ufs/host/ufshcd-dwc.c | 6 ++++--
drivers/ufs/host/ufshcd-dwc.h | 2 ++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/ufs/host/ufshcd-dwc.c b/drivers/ufs/host/ufshcd-dwc.c
index 0eceec543d14..7fe54923c6c6 100644
--- a/drivers/ufs/host/ufshcd-dwc.c
+++ b/drivers/ufs/host/ufshcd-dwc.c
@@ -39,10 +39,11 @@ EXPORT_SYMBOL(ufshcd_dwc_dme_set_attrs);
* @divider_val: clock divider value to be programmed
*
*/
-static void ufshcd_dwc_program_clk_div(struct ufs_hba *hba, u32 divider_val)
+void ufshcd_dwc_program_clk_div(struct ufs_hba *hba, u32 divider_val)
{
ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV);
}
+EXPORT_SYMBOL(ufshcd_dwc_program_clk_div);
/**
* ufshcd_dwc_link_is_up() - check if link is up.
@@ -50,7 +51,7 @@ static void ufshcd_dwc_program_clk_div(struct ufs_hba *hba, u32 divider_val)
*
* Return: 0 on success, non-zero value on failure.
*/
-static int ufshcd_dwc_link_is_up(struct ufs_hba *hba)
+int ufshcd_dwc_link_is_up(struct ufs_hba *hba)
{
int dme_result = 0;
@@ -63,6 +64,7 @@ static int ufshcd_dwc_link_is_up(struct ufs_hba *hba)
return 1;
}
+EXPORT_SYMBOL(ufshcd_dwc_link_is_up);
/**
* ufshcd_dwc_connection_setup() - configure unipro attributes.
diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h
index d8673cd54d4c..53b523ef59df 100644
--- a/drivers/ufs/host/ufshcd-dwc.h
+++ b/drivers/ufs/host/ufshcd-dwc.h
@@ -47,4 +47,6 @@ int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
const struct ufshcd_dme_attr_val *v, int n);
int ufshcd_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val);
int ufshcd_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val);
+int ufshcd_dwc_link_is_up(struct ufs_hba *hba);
+void ufshcd_dwc_program_clk_div(struct ufs_hba *hba, u32 divider_val);
#endif /* End of Header */
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v3 06/10] dt-bindings: ufs: Add NXP S32N79 UFS host controller
2026-09-16 8:44 [PATCH v3 00/10] Add S32N79RDB UFS support Larisa Grigore
` (4 preceding siblings ...)
2026-09-16 8:44 ` [PATCH v3 05/10] scsi: ufs: dwc: Export common clock divider and link status helpers Larisa Grigore
@ 2026-09-16 8:44 ` Larisa Grigore
2026-09-16 16:34 ` Frank Li
2026-09-16 8:44 ` [PATCH v3 07/10] scsi: ufs: Add NXP S32N79 UFS host controller driver Larisa Grigore
` (3 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Larisa Grigore @ 2026-09-16 8:44 UTC (permalink / raw)
To: Larisa Grigore, NXP S32 Linux Team, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa
Cc: linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
Document the UFS host controller on the NXP S32N79 SoC.
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
---
.../bindings/ufs/nxp,s32n79-ufshc.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml
diff --git a/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml b/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml
new file mode 100644
index 000000000000..2bede50a9b6f
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/nxp,s32n79-ufshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP S32N79 Universal Flash Storage (UFS) Controller
+
+maintainers:
+ - Larisa Grigore <larisa.grigore@oss.nxp.com>
+
+# Select only our matches, not all jedec,ufs
+select:
+ properties:
+ compatible:
+ contains:
+ const: nxp,s32n79-ufshc
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: nxp,s32n79-ufshc
+ - const: jedec,ufs-2.0
+
+ reg:
+ items:
+ - description: UFS Host Controller registers
+ - description: System Control Module registers
+
+ reg-names:
+ items:
+ - const: ufshc
+ - const: scm
+
+ clocks:
+ maxItems: 1
+ description: UFS core clock
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+
+allOf:
+ - $ref: ufs-common.yaml
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ ufshc@4ac80000 {
+ compatible = "nxp,s32n79-ufshc", "jedec,ufs-2.0";
+ reg = <0x4ac80000 0x1000>, <0x4ac40000 0x1000>;
+ reg-names = "ufshc", "scm";
+ interrupt-parent = <&irqsteer_coss>;
+ interrupts = <211>;
+ clocks = <&clks 0x92>;
+ };
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 06/10] dt-bindings: ufs: Add NXP S32N79 UFS host controller
2026-09-16 8:44 ` [PATCH v3 06/10] dt-bindings: ufs: Add NXP S32N79 UFS host controller Larisa Grigore
@ 2026-09-16 16:34 ` Frank Li
0 siblings, 0 replies; 17+ messages in thread
From: Frank Li @ 2026-09-16 16:34 UTC (permalink / raw)
To: Larisa Grigore
Cc: NXP S32 Linux Team, Alim Akhtar, Avri Altman, Bart Van Assche,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa ,
linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
On Wed, Sep 16, 2026 at 10:44:07AM +0200, Larisa Grigore wrote:
> Document the UFS host controller on the NXP S32N79 SoC.
>
> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
> ---
> .../bindings/ufs/nxp,s32n79-ufshc.yaml | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml
>
> diff --git a/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml b/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml
> new file mode 100644
> index 000000000000..2bede50a9b6f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/ufs/nxp,s32n79-ufshc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP S32N79 Universal Flash Storage (UFS) Controller
> +
> +maintainers:
> + - Larisa Grigore <larisa.grigore@oss.nxp.com>
> +
> +# Select only our matches, not all jedec,ufs
> +select:
> + properties:
> + compatible:
> + contains:
> + const: nxp,s32n79-ufshc
> + required:
> + - compatible
> +
> +properties:
> + compatible:
> + items:
> + - const: nxp,s32n79-ufshc
> + - const: jedec,ufs-2.0
I have not seen driver parse it even though other vendor use it at dts
and yaml.
leave dt team to comment it.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> +
> + reg:
> + items:
> + - description: UFS Host Controller registers
> + - description: System Control Module registers
> +
> + reg-names:
> + items:
> + - const: ufshc
> + - const: scm
> +
> + clocks:
> + maxItems: 1
> + description: UFS core clock
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> +
> +allOf:
> + - $ref: ufs-common.yaml
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + ufshc@4ac80000 {
> + compatible = "nxp,s32n79-ufshc", "jedec,ufs-2.0";
> + reg = <0x4ac80000 0x1000>, <0x4ac40000 0x1000>;
> + reg-names = "ufshc", "scm";
> + interrupt-parent = <&irqsteer_coss>;
> + interrupts = <211>;
> + clocks = <&clks 0x92>;
> + };
> --
> 2.43.0\
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 07/10] scsi: ufs: Add NXP S32N79 UFS host controller driver
2026-09-16 8:44 [PATCH v3 00/10] Add S32N79RDB UFS support Larisa Grigore
` (5 preceding siblings ...)
2026-09-16 8:44 ` [PATCH v3 06/10] dt-bindings: ufs: Add NXP S32N79 UFS host controller Larisa Grigore
@ 2026-09-16 8:44 ` Larisa Grigore
2026-09-16 8:44 ` [PATCH v3 08/10] arm64: dts: freescale: s32n79: Add UFS host controller Larisa Grigore
` (2 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Larisa Grigore @ 2026-09-16 8:44 UTC (permalink / raw)
To: Larisa Grigore, NXP S32 Linux Team, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa
Cc: linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
Add support for the UFS host controller on the NXP S32N79 SoC, built on
the Synopsys DesignWare (DWC) UFS architecture, using the UFSHCD DWC and
UFSHCD platform glue.
This controller requires S32N79-specific initialization prior to
UIC_LINKSTARTUP, including:
- programming SCM.ONE_US_TICK and HC.HCLKDIV based on the core clock,
- applying the vendor-defined M-PHY calibration sequence, and
- performing post-link calibration steps needed for HS operation.
The M-PHY supports several boot modes for loading its firmware. Only the
mode where the firmware runs from the internal ROM is supported for now.
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
---
drivers/ufs/host/Kconfig | 12 +
drivers/ufs/host/Makefile | 1 +
drivers/ufs/host/ufs-nxp-s32n7.c | 543 +++++++++++++++++++++++++++++++
drivers/ufs/host/ufshcd-dwc.h | 14 +-
drivers/ufs/host/ufshci-dwc.h | 6 +
5 files changed, 574 insertions(+), 2 deletions(-)
create mode 100644 drivers/ufs/host/ufs-nxp-s32n7.c
diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig
index ff170c0b6da0..e8ee7dd05f1a 100644
--- a/drivers/ufs/host/Kconfig
+++ b/drivers/ufs/host/Kconfig
@@ -168,3 +168,15 @@ config SCSI_UFS_AMD_VERSAL2
Select this if you have UFS controller on AMD Versal Gen 2 SoC.
If unsure, say N.
+
+config SCSI_UFS_S32N7
+ tristate "NXP S32N7 platform driver"
+ depends on SCSI_UFSHCD_PLATFORM && (ARCH_S32 || COMPILE_TEST)
+ help
+ This selects the S32N7 specific additions on top of the UFSHCD DWC
+ and UFSHCD platform driver. UFS host on S32N79 needs some vendor
+ specific configurations like PHY and vendor specific register accesses
+ before accessing the hardware.
+
+ Select this if you have UFS controller on an S32N7 based board.
+ If unsure, say N.
diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile
index 7d8db67eb23c..a2f4a1d0b3ae 100644
--- a/drivers/ufs/host/Makefile
+++ b/drivers/ufs/host/Makefile
@@ -4,6 +4,7 @@ CONTEXT_ANALYSIS := y
obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210.o
obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o
+obj-$(CONFIG_SCSI_UFS_S32N7) += ufs-nxp-s32n7.o ufshcd-dwc.o
obj-$(CONFIG_SCSI_UFS_CDNS_PLATFORM) += cdns-pltfrm.o
obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o
diff --git a/drivers/ufs/host/ufs-nxp-s32n7.c b/drivers/ufs/host/ufs-nxp-s32n7.c
new file mode 100644
index 000000000000..4f9a00156202
--- /dev/null
+++ b/drivers/ufs/host/ufs-nxp-s32n7.c
@@ -0,0 +1,543 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright 2026 NXP
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+
+#include "ufshcd-pltfrm.h"
+#include "ufshcd-dwc.h"
+#include "ufshci-dwc.h"
+
+/* SCM Register Offsets. */
+#define SCM_ONE_US_TICK 0x2CU
+#define SCM_STATUS 0x30
+
+/* SCM_ONE_US_TICK Register. */
+#define SCM_ONE_US_TICK_MASK GENMASK(8, 0)
+
+/* SCM_MPHY_RAM_CONFIG_STATUS Register Fields. */
+#define SCM_STATUS_PHY_RESET_MASK BIT(0)
+#define SCM_STATUS_SRAM_BYPASS_MASK BIT(1)
+#define SCM_STATUS_SRAM_INIT_DONE_MASK BIT(16)
+
+#define SCM_STATUS_PHY_RESET(val) \
+ FIELD_PREP(SCM_STATUS_PHY_RESET_MASK, val)
+
+#define SCM_STATUS_SRAM_BYPASS(val) \
+ FIELD_PREP(SCM_STATUS_SRAM_BYPASS_MASK, val)
+
+/* Timeout values. */
+#define CFG_MPHY_INIT_TIMEOUT_VALUE_US 3000000
+
+/* Clock validation limits. */
+#define MAX_VALID_ONE_US_TICK SCM_ONE_US_TICK_MASK
+
+/* CPort definitions */
+#define CPORT_0 0
+
+/* Driver-defined timeout for completing a Hibern8 transition. */
+#define HBRN8_POLL_TOUT_MS 1000
+
+/**
+ * struct s32n7_phy_reg - PHY CR (config-register) write entry
+ * @reg: Register offset/address
+ * @val: Value to write
+ */
+struct s32n7_phy_reg {
+ u32 reg;
+ u32 val;
+};
+
+/**
+ * struct s32n7_soc_data - SoC-specific configuration data
+ * @vops: UFS host controller variant operations
+ * @reset_config: MPHY reset DME attributes (programmed while PHY held in reset)
+ * @reset_config_count: number of entries in @reset_config
+ * @calib_mphy_disabled: CR calibration writes performed while the MPHY is disabled
+ * @calib_mphy_disabled_count: number of entries in @calib_mphy_disabled
+ * @calib_mphy_enabled: CR calibration writes performed while the MPHY is enabled
+ * @calib_mphy_enabled_count: number of entries in @calib_mphy_enabled
+ */
+struct s32n7_soc_data {
+ const struct ufs_hba_variant_ops *vops;
+ const struct ufshcd_dme_attr_val *reset_config;
+ size_t reset_config_count;
+ const struct s32n7_phy_reg *calib_mphy_disabled;
+ size_t calib_mphy_disabled_count;
+ const struct s32n7_phy_reg *calib_mphy_enabled;
+ size_t calib_mphy_enabled_count;
+};
+
+/**
+ * struct s32n7_ufs - S32N7 UFS host controller data
+ * @hba: UFS host controller instance
+ * @reg_scm: SCM register base address
+ * @core_clk: core reference clock used to derive ONE_US_TICK/HCLKDIV
+ * @soc_data: SoC-specific configuration data
+ */
+struct s32n7_ufs {
+ struct ufs_hba *hba;
+ void __iomem *reg_scm;
+ struct clk *core_clk;
+ const struct s32n7_soc_data *soc_data;
+};
+
+/**
+ * ufs_s32n7_phy_write_sequence - Write a sequence of PHY registers
+ * @hba: UFS host controller instance
+ * @cfg: Array of register configurations
+ * @count: Number of entries in the array
+ *
+ * Return: 0 on success, error code on failure
+ */
+static int ufs_s32n7_phy_write_sequence(struct ufs_hba *hba,
+ const struct s32n7_phy_reg *cfg,
+ size_t count)
+{
+ int ret;
+ size_t i;
+
+ for (i = 0; i < count; i++) {
+ ret = ufshcd_dwc_phy_reg_write(hba, cfg[i].reg, cfg[i].val);
+ if (ret) {
+ dev_err(hba->dev,
+ "Failed to write PHY reg 0x%x = 0x%x (step %zu)\n",
+ cfg[i].reg, cfg[i].val, i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static unsigned long ufs_s32n7_calculate_us_tick(unsigned long clk_rate)
+{
+ return clk_rate / USEC_PER_SEC;
+}
+
+static int ufs_s32n7_configure_clocks(struct ufs_hba *hba)
+{
+ struct s32n7_ufs *ufs = ufshcd_get_variant(hba);
+ struct device *dev = hba->dev;
+ unsigned long clk_rate = 0;
+ unsigned long one_us_tick;
+
+ clk_rate = clk_get_rate(ufs->core_clk);
+ if (!clk_rate) {
+ dev_err(dev, "Failed to get valid clock rate.\n");
+ return -EINVAL;
+ }
+
+ one_us_tick = ufs_s32n7_calculate_us_tick(clk_rate);
+ if (one_us_tick == 0 || one_us_tick > MAX_VALID_ONE_US_TICK) {
+ dev_err(dev, "Invalid one_us_tick value: %lu (clk_rate: %lu Hz).\n",
+ one_us_tick, clk_rate);
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "Core clock rate: %lu Hz, one_us_tick = %lu.\n",
+ clk_rate, one_us_tick);
+
+ /*
+ * Configure the micro-second tick rate generator based on core
+ * clock rate.
+ */
+ writel(one_us_tick, ufs->reg_scm + SCM_ONE_US_TICK);
+ ufshcd_dwc_program_clk_div(hba, one_us_tick);
+
+ return 0;
+}
+
+static int ufs_s32n7_hce_enable_notify(struct ufs_hba *hba,
+ enum ufs_notify_change_status status)
+{
+ u32 reg;
+
+ if (status != POST_CHANGE)
+ return 0;
+
+ /*
+ * Clear the DWC low-power gating (BUSTHRTL) so a doorbell write can
+ * wake the link out of hibernate. LP_PGE (generic low-power) and
+ * LP_AH8_PGE (Auto-Hibern8) both reset to 1.
+ */
+ reg = ufshcd_readl(hba, DWC_UFS_REG_BUSTHRTL);
+ reg &= ~(DWC_UFS_BUSTHRTL_LP_PGE | DWC_UFS_BUSTHRTL_LP_AH8_PGE);
+ ufshcd_writel(hba, reg, DWC_UFS_REG_BUSTHRTL);
+
+ return 0;
+}
+
+static int ufs_s32n7_phy_initial_calib(struct ufs_hba *hba)
+{
+ struct s32n7_ufs *ufs = ufshcd_get_variant(hba);
+ int ret;
+
+ /* Calibrations that must run while the MPHY is disabled. */
+ ret = ufs_s32n7_phy_write_sequence(hba, ufs->soc_data->calib_mphy_disabled,
+ ufs->soc_data->calib_mphy_disabled_count);
+ if (ret)
+ return ret;
+
+ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VS_MPHYCFGUPDT, 0), 0x1);
+ if (ret)
+ return ret;
+
+ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VS_MPHYDISABLE, 0), 0x0);
+ if (ret)
+ return ret;
+
+ /* Calibrations that must run while the MPHY is enabled. */
+ ret = ufs_s32n7_phy_write_sequence(hba, ufs->soc_data->calib_mphy_enabled,
+ ufs->soc_data->calib_mphy_enabled_count);
+ if (ret)
+ return ret;
+
+ return ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VS_MPHYCFGUPDT, 0), 0x1);
+}
+
+static int ufs_s32n7_link_startup_pre_change(struct ufs_hba *hba)
+{
+ struct s32n7_ufs *ufs = ufshcd_get_variant(hba);
+ struct device *dev = hba->dev;
+ int ret;
+ u32 reg;
+
+ ret = ufs_s32n7_configure_clocks(hba);
+ if (ret)
+ return ret;
+
+ /* Reset SCM.MPHY_RAM_CONFIG_STATUS to default value; keep MPHY in reset. */
+ writel(SCM_STATUS_PHY_RESET(1), ufs->reg_scm + SCM_STATUS);
+
+ /*
+ * The M-PHY firmware runs from the internal ROM:
+ * MPHY_RAM_CONFIG_STATUS.SRAM_BYPASS = 1
+ * MPHY_RAM_CONFIG_STATUS.SRAM_EXT_LD_DONE = 0
+ */
+ writel(SCM_STATUS_PHY_RESET(1) | SCM_STATUS_SRAM_BYPASS(1),
+ ufs->reg_scm + SCM_STATUS);
+
+ /* MPHY reset configuration: vendor attributes set while PHY in reset. */
+ ret = ufshcd_dwc_dme_set_attrs(hba, ufs->soc_data->reset_config,
+ ufs->soc_data->reset_config_count);
+ if (ret)
+ return ret;
+
+ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VS_MPHYCFGUPDT, 0), 0x1);
+ if (ret)
+ return ret;
+
+ /* Release PHY_RESET. */
+ writel(readl(ufs->reg_scm + SCM_STATUS) & ~SCM_STATUS_PHY_RESET_MASK,
+ ufs->reg_scm + SCM_STATUS);
+
+ /* Wait until SRAM_INIT_DONE = 1. */
+ ret = readl_poll_timeout(ufs->reg_scm + SCM_STATUS, reg,
+ reg & SCM_STATUS_SRAM_INIT_DONE_MASK,
+ 1000, CFG_MPHY_INIT_TIMEOUT_VALUE_US);
+ if (ret) {
+ dev_err(dev, "UFS MPHY init not done!\n");
+ return ret;
+ }
+
+ /* Start of initial calibration */
+ ret = ufs_s32n7_phy_initial_calib(hba);
+ if (ret) {
+ dev_err(dev, "UFS MPHY initial calibration failed!\n");
+ return ret;
+ }
+
+ /* End of Gear1 settings */
+
+ return ufshcd_dme_check_tx_hibern8(hba, hba->lanes_per_direction,
+ HBRN8_POLL_TOUT_MS);
+}
+
+static int ufs_s32n7_link_startup_post_change(struct ufs_hba *hba)
+{
+ static const struct ufshcd_dme_attr_val cport_setup[] = {
+ { UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, CPORT_0),
+ CPORT_IDLE, DME_LOCAL },
+ { UIC_ARG_MIB_SEL(T_CPORTFLAGS, CPORT_0),
+ CPORT_DEF_FLAGS, DME_LOCAL },
+ { UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, CPORT_0),
+ CPORT_CONNECTED, DME_LOCAL },
+ };
+ unsigned int data = 0;
+ int ret;
+
+ /* Network layer: set Local DeviceID. */
+ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID, 0), 0x0);
+ if (ret)
+ return ret;
+
+ /* Set Connection State to IDLE (it allows CPort Attributes to be set). */
+ ret = ufshcd_dwc_dme_set_attrs(hba, cport_setup, ARRAY_SIZE(cport_setup));
+ if (ret)
+ return ret;
+
+ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, CPORT_0), &data);
+ if (ret)
+ return ret;
+
+ if (data != CPORT_CONNECTED)
+ return -EIO;
+
+ return 0;
+}
+
+static int ufs_s32n7_link_startup_notify(struct ufs_hba *hba,
+ enum ufs_notify_change_status status)
+{
+ int err;
+
+ if (status == PRE_CHANGE) {
+ err = ufs_s32n7_link_startup_pre_change(hba);
+ if (err) {
+ dev_err(hba->dev, "MPHY setup failed (%d).\n", err);
+ return err;
+ }
+ return 0;
+ }
+
+ /* POST_CHANGE */
+ err = ufshcd_dwc_link_is_up(hba);
+ if (err) {
+ dev_err(hba->dev, "Link is not up.\n");
+ return err;
+ }
+
+ err = ufs_s32n7_link_startup_post_change(hba);
+ if (err)
+ dev_err(hba->dev, "Connection setup failed (%d).\n", err);
+
+ return err;
+}
+
+static int ufs_s32n7_pwr_change_pre_change(struct ufs_hba *hba,
+ const struct ufs_pa_layer_attr *pwr)
+{
+ /*
+ * RX rate-select override sequence: assert the override, then deassert
+ * the value, then drop the override enable so normal operation resumes.
+ */
+ static const struct s32n7_phy_reg pwr_change_phy_regs[] = {
+ { RX_OVRD_IN_1(0), 0xc },
+ { RX_OVRD_IN_1(1), 0xc },
+ { RX_OVRD_IN_1(0), 0x8 },
+ { RX_OVRD_IN_1(1), 0x8 },
+ { RX_OVRD_IN_1(0), 0x0 },
+ { RX_OVRD_IN_1(1), 0x0 },
+ };
+ u32 rate;
+ int ret;
+
+ /* Rate change only applies to the HS power modes. */
+ if (!ufshcd_is_hs_mode(pwr))
+ return 0;
+
+ /*
+ * Select the M-PHY rate (rate series) that matches the mode the core
+ * has negotiated with the device.
+ */
+ rate = (pwr->hs_rate == PA_HS_MODE_B) ? CB_RATE_B : CB_RATE_A;
+
+ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(CBRATESEL, 0), rate);
+ if (ret)
+ return ret;
+
+ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VS_MPHYCFGUPDT, 0), 0x1);
+ if (ret)
+ return ret;
+
+ /* Apply the RX rate-select override now that the target rate is set. */
+ return ufs_s32n7_phy_write_sequence(hba, pwr_change_phy_regs,
+ ARRAY_SIZE(pwr_change_phy_regs));
+}
+
+static int ufs_s32n7_pwr_change_notify(struct ufs_hba *hba,
+ enum ufs_notify_change_status status,
+ struct ufs_pa_layer_attr *pwr)
+{
+ int err = 0;
+
+ if (status == PRE_CHANGE) {
+ err = ufs_s32n7_pwr_change_pre_change(hba, pwr);
+ if (err)
+ dev_err(hba->dev, "Power mode pre-change failed (%d).\n",
+ err);
+ }
+
+ return err;
+}
+
+static int ufs_s32n7_init(struct ufs_hba *hba)
+{
+ struct device *dev = hba->dev;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct s32n7_ufs *ufs;
+
+ ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
+ if (!ufs)
+ return -ENOMEM;
+
+ ufs->hba = hba;
+ ufs->soc_data = device_get_match_data(dev);
+ if (!ufs->soc_data)
+ return -ENODEV;
+
+ hba->quirks |= UFSHCD_QUIRK_PERFORM_LINK_STARTUP_ONCE;
+ hba->spm_lvl = UFS_PM_LVL_5;
+
+ ufs->reg_scm = devm_platform_ioremap_resource_byname(pdev, "scm");
+ if (IS_ERR(ufs->reg_scm))
+ return dev_err_probe(dev, PTR_ERR(ufs->reg_scm),
+ "ioremap failed for SCM registers.\n");
+
+ /*
+ * The core reference clock is not managed by the UFS core (the DT node
+ * has no clock-names/freq-table-hz, so it is never added to
+ * hba->clk_list_head).
+ */
+ ufs->core_clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(ufs->core_clk))
+ return dev_err_probe(dev, PTR_ERR(ufs->core_clk),
+ "Failed to get and enable core clock.\n");
+
+ ufshcd_set_variant(hba, ufs);
+
+ return 0;
+}
+
+static const struct ufs_hba_variant_ops ufs_hba_s32n79_vops = {
+ .name = "s32n79",
+ .init = ufs_s32n7_init,
+ .link_startup_notify = ufs_s32n7_link_startup_notify,
+ .hce_enable_notify = ufs_s32n7_hce_enable_notify,
+ .pwr_change_notify = ufs_s32n7_pwr_change_notify,
+};
+
+/*
+ * MPHY reset configuration: vendor DME attributes programmed while the PHY is
+ * held in reset. Programs the reference-clock, RX squelch, RX Rhold and
+ * CR-parallel control attributes.
+ */
+static const struct ufshcd_dme_attr_val s32n79_reset_config[] = {
+ /*
+ * Disable reference clock gating support and override the UniPro and
+ * application reference clock enable inputs to 0.
+ */
+ { UIC_ARG_MIB_SEL(CBREFCLKCTRL2, 0), 0x8A, DME_LOCAL },
+ /* RX squelch control. */
+ { UIC_ARG_MIB_SEL(RXSQCONTROL, SELIND_LN0_RX), 0x1, DME_LOCAL },
+ { UIC_ARG_MIB_SEL(RXSQCONTROL, SELIND_LN1_RX), 0x1, DME_LOCAL },
+ /* RX Rhold control option. */
+ { UIC_ARG_MIB_SEL(RXRHOLDCTRLOPT, SELIND_LN0_RX), 0x2, DME_LOCAL },
+ { UIC_ARG_MIB_SEL(RXRHOLDCTRLOPT, SELIND_LN1_RX), 0x2, DME_LOCAL },
+ /* CR parallel selection. */
+ { UIC_ARG_MIB_SEL(CBCRCTRL, 0), 0x1, DME_LOCAL },
+};
+
+/* Calibrations that must run while the MPHY is disabled. */
+static const struct s32n7_phy_reg s32n79_calib_mphy_disabled[] = {
+ /* Bypass RX AFE calibration. */
+ { FAST_FLAGS(0), 0x4 },
+ { FAST_FLAGS(1), 0x4 },
+};
+
+/* Calibrations that must run while the MPHY is enabled. */
+static const struct s32n7_phy_reg s32n79_calib_mphy_enabled[] = {
+ /* Write ATT offset compensation code to internal DAC. */
+ { RX_DAC_CTRL_OVRD(0), 0x1 },
+ { RX_DAC_CTRL_OVRD(1), 0x1 },
+ { RX_DAC_CTRL(0), 0x8E },
+ { RX_DAC_CTRL(1), 0x91 },
+ { RX_DAC_CTRL_SEL(0), 0x1 },
+ { RX_DAC_CTRL_SEL(1), 0x1 },
+ { RX_DAC_CTRL_EN(0), 0x1 },
+ { RX_DAC_CTRL_EN(1), 0x1 },
+ { RX_DAC_CTRL_OVRD(0), 0x0 },
+ { RX_DAC_CTRL_OVRD(1), 0x0 },
+ /* Write CTLE offset compensation code to internal DAC. */
+ { RX_DAC_CTRL_OVRD(0), 0x1 },
+ { RX_DAC_CTRL_OVRD(1), 0x1 },
+ { RX_DAC_CTRL(0), 0x71 },
+ { RX_DAC_CTRL(1), 0x7F },
+ { RX_DAC_CTRL_SEL(0), 0x2 },
+ { RX_DAC_CTRL_SEL(1), 0x2 },
+ { RX_DAC_CTRL_EN(0), 0x1 },
+ { RX_DAC_CTRL_EN(1), 0x1 },
+ { RX_DAC_CTRL_OVRD(0), 0x0 },
+ { RX_DAC_CTRL_OVRD(1), 0x0 },
+ /* FW Calibration configuration. */
+ { FW_CALIB_CCFG(0), 0x100 },
+ { FW_CALIB_CCFG(1), 0x100 },
+};
+
+static const struct s32n7_soc_data s32n79_soc_data = {
+ .vops = &ufs_hba_s32n79_vops,
+ .reset_config = s32n79_reset_config,
+ .reset_config_count = ARRAY_SIZE(s32n79_reset_config),
+ .calib_mphy_disabled = s32n79_calib_mphy_disabled,
+ .calib_mphy_disabled_count = ARRAY_SIZE(s32n79_calib_mphy_disabled),
+ .calib_mphy_enabled = s32n79_calib_mphy_enabled,
+ .calib_mphy_enabled_count = ARRAY_SIZE(s32n79_calib_mphy_enabled),
+};
+
+static const struct of_device_id ufs_s32n7_match[] = {
+ {
+ .compatible = "nxp,s32n79-ufshc",
+ .data = &s32n79_soc_data,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ufs_s32n7_match);
+
+static int ufs_s32n7_probe(struct platform_device *pdev)
+{
+ const struct s32n7_soc_data *soc_data;
+
+ soc_data = device_get_match_data(&pdev->dev);
+ if (!soc_data)
+ return -ENODEV;
+
+ return ufshcd_pltfrm_init(pdev, soc_data->vops);
+}
+
+static void ufs_s32n7_remove(struct platform_device *pdev)
+{
+ ufshcd_pltfrm_remove(pdev);
+}
+
+static const struct dev_pm_ops ufs_s32n7_pm_ops = {
+ SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
+ RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
+ .prepare = ufshcd_suspend_prepare,
+ .complete = ufshcd_resume_complete,
+};
+
+static struct platform_driver ufs_s32n7_driver = {
+ .probe = ufs_s32n7_probe,
+ .remove = ufs_s32n7_remove,
+ .driver = {
+ .name = "ufs-s32n7",
+ .pm = pm_ptr(&ufs_s32n7_pm_ops),
+ .of_match_table = ufs_s32n7_match,
+ },
+};
+
+module_platform_driver(ufs_s32n7_driver);
+
+MODULE_AUTHOR("Larisa Grigore <larisa.grigore@oss.nxp.com>");
+MODULE_DESCRIPTION("NXP S32N7 UFS Host Controller platform driver");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h
index 53b523ef59df..d62cd4c085ba 100644
--- a/drivers/ufs/host/ufshcd-dwc.h
+++ b/drivers/ufs/host/ufshcd-dwc.h
@@ -13,8 +13,8 @@
#include <ufs/ufshcd.h>
/* RMMI Attributes */
-#define CBREFCLKCTRL2 0x8132
-#define CBCRCTRL 0x811F
+#define RXSQCONTROL 0x8009
+#define RXRHOLDCTRLOPT 0x8013
#define CBC10DIRECTCONF2 0x810E
#define CBRATESEL 0x8114
#define CBCREGADDRLSB 0x8116
@@ -24,10 +24,20 @@
#define CBCREGRDLSB 0x811A
#define CBCREGRDMSB 0x811B
#define CBCREGRDWRSEL 0x811C
+#define CBCRCTRL 0x811F
+#define CBREFCLKCTRL2 0x8132
#define CBREFREFCLK_GATE_OVR_EN BIT(7)
+/* CBRATESEL: 0 - rate A, 1 - rate B. */
+#define CB_RATE_A 0x0
+#define CB_RATE_B 0x1
+
/* M-PHY registers */
+#define RX_DAC_CTRL(n) (0x10AF + ((n) * 0x100))
+#define RX_DAC_CTRL_OVRD(n) (0x10B0 + ((n) * 0x100))
+#define RX_DAC_CTRL_SEL(n) (0x10B1 + ((n) * 0x100))
+#define RX_DAC_CTRL_EN(n) (0x10B8 + ((n) * 0x100))
#define RX_OVRD_IN_1(n) (0x3006 + ((n) * 0x100))
#define RX_PCS_OUT(n) (0x300F + ((n) * 0x100))
#define FAST_FLAGS(n) (0x401C + ((n) * 0x100))
diff --git a/drivers/ufs/host/ufshci-dwc.h b/drivers/ufs/host/ufshci-dwc.h
index 6c290e272106..c66f33391b65 100644
--- a/drivers/ufs/host/ufshci-dwc.h
+++ b/drivers/ufs/host/ufshci-dwc.h
@@ -12,9 +12,15 @@
/* DWC HC UFSHCI specific Registers */
enum dwc_specific_registers {
+ DWC_UFS_REG_BUSTHRTL = 0xC0,
DWC_UFS_REG_HCLKDIV = 0xFC,
};
+/* Low-Power Power Gating Enable. */
+#define DWC_UFS_BUSTHRTL_LP_PGE BIT(16)
+/* Low Power - AH8 Power Gating Enable. */
+#define DWC_UFS_BUSTHRTL_LP_AH8_PGE BIT(17)
+
/* Clock Divider Values: Hex equivalent of frequency in MHz */
enum clk_div_values {
DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e,
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v3 08/10] arm64: dts: freescale: s32n79: Add UFS host controller
2026-09-16 8:44 [PATCH v3 00/10] Add S32N79RDB UFS support Larisa Grigore
` (6 preceding siblings ...)
2026-09-16 8:44 ` [PATCH v3 07/10] scsi: ufs: Add NXP S32N79 UFS host controller driver Larisa Grigore
@ 2026-09-16 8:44 ` Larisa Grigore
2026-09-16 8:44 ` [PATCH v3 09/10] arm64: dts: freescale: s32n79-rdb: Enable UFS Larisa Grigore
2026-09-16 8:44 ` [PATCH v3 10/10] MAINTAINERS: Add NXP S32N7 UFS host controller entry Larisa Grigore
9 siblings, 0 replies; 17+ messages in thread
From: Larisa Grigore @ 2026-09-16 8:44 UTC (permalink / raw)
To: Larisa Grigore, NXP S32 Linux Team, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa
Cc: linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
Add the S32N79 UFS host controller node to the SoC dtsi.
The controller remains disabled by default and is enabled by board dts
files as needed.
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32n79.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dts/freescale/s32n79.dtsi
index 94ab58783fdc..0b51ca8bc7f9 100644
--- a/arch/arm64/boot/dts/freescale/s32n79.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi
@@ -100,6 +100,16 @@ uart7: serial@4aa40000 {
status = "disabled";
};
+ ufshc: ufs@4ac80000 {
+ compatible = "nxp,s32n79-ufshc", "jedec,ufs-2.0";
+ reg = <0x4ac80000 0x1000>, <0x4ac40000 0x1000>;
+ reg-names = "ufshc", "scm";
+ interrupt-parent = <&irqsteer_coss>;
+ interrupts = <211>;
+ clocks = <&clks 0x92>;
+ status = "disabled";
+ };
+
irqsteer_coss: interrupt-controller@4ed00000 {
compatible = "nxp,s32n79-irqsteer";
reg = <0x4ed00000 0x10000>;
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v3 09/10] arm64: dts: freescale: s32n79-rdb: Enable UFS
2026-09-16 8:44 [PATCH v3 00/10] Add S32N79RDB UFS support Larisa Grigore
` (7 preceding siblings ...)
2026-09-16 8:44 ` [PATCH v3 08/10] arm64: dts: freescale: s32n79: Add UFS host controller Larisa Grigore
@ 2026-09-16 8:44 ` Larisa Grigore
2026-09-16 8:44 ` [PATCH v3 10/10] MAINTAINERS: Add NXP S32N7 UFS host controller entry Larisa Grigore
9 siblings, 0 replies; 17+ messages in thread
From: Larisa Grigore @ 2026-09-16 8:44 UTC (permalink / raw)
To: Larisa Grigore, NXP S32 Linux Team, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa
Cc: linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
Enable the UFS host controller on the S32N79 RDB and configure it for
two lanes per direction.
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32n79-rdb.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32n79-rdb.dts b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts
index 1feccd61258e..38c5699e6d54 100644
--- a/arch/arm64/boot/dts/freescale/s32n79-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts
@@ -63,6 +63,11 @@ &uart7 {
status = "okay";
};
+&ufshc {
+ lanes-per-direction = <2>;
+ status = "okay";
+};
+
&usdhc0 {
disable-wp;
no-sdio;
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v3 10/10] MAINTAINERS: Add NXP S32N7 UFS host controller entry
2026-09-16 8:44 [PATCH v3 00/10] Add S32N79RDB UFS support Larisa Grigore
` (8 preceding siblings ...)
2026-09-16 8:44 ` [PATCH v3 09/10] arm64: dts: freescale: s32n79-rdb: Enable UFS Larisa Grigore
@ 2026-09-16 8:44 ` Larisa Grigore
9 siblings, 0 replies; 17+ messages in thread
From: Larisa Grigore @ 2026-09-16 8:44 UTC (permalink / raw)
To: Larisa Grigore, NXP S32 Linux Team, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
James E.J. Bottomley, Martin K. Petersen, Sai Krishna Potthuri,
Ajay Neeli, Manivannan Sadhasivam, Pedro Sousa
Cc: linux-scsi, devicetree, linux-kernel, imx, linux-arm-kernel,
linux-arm-msm, clizzi, aruizrui, eballetb, echanude
Add maintainer for S32N7 UFS host controller driver.
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3b2eb2a7a89a..32b01db895f9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -28096,6 +28096,14 @@ L: linux-scsi@vger.kernel.org
S: Maintained
F: drivers/ufs/host/ufs-renesas.c
+UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER S32N7 HOOKS
+M: Larisa Grigore <larisa.grigore@oss.nxp.com>
+R: NXP S32 Linux Team <s32@nxp.com>
+L: linux-scsi@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml
+F: drivers/ufs/host/ufs-nxp-s32n7.c
+
UNIWILL LAPTOP DRIVER
M: Armin Wolf <W_Armin@gmx.de>
L: platform-driver-x86@vger.kernel.org
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread