From: Richard Cheng <icheng@nvidia.com>
To: mhonap@nvidia.com
Cc: alex@shazbot.org, jgg@ziepe.ca, ankita@nvidia.com,
jic23@kernel.org, dave.jiang@intel.com,
alejandro.lucero-palau@amd.com, smadhavan@nvidia.com,
corbet@lwn.net, skhan@linuxfoundation.org, dave@stgolabs.net,
alison.schofield@intel.com, vishal.l.verma@intel.com,
iweiny@kernel.org, ming.li@zohomail.com, yishaih@nvidia.com,
skolothumtho@nvidia.com, kevin.tian@intel.com,
bhelgaas@google.com, dmatlack@google.com, kees@kernel.org,
gustavoars@kernel.org, cjia@nvidia.com, kjaju@nvidia.com,
vsethi@nvidia.com, zhiw@nvidia.com, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kselftest@vger.kernel.org,
linux-hardening@vger.kernel.org
Subject: Re: [PATCH v5 21/27] vfio/cxl: Exclude the HDM decoder registers from direct BAR access
Date: Thu, 17 Sep 2026 15:28:44 +0800 [thread overview]
Message-ID: <aquVEF7pLCpQxYwa@MWDK4CY14F> (raw)
In-Reply-To: <20260916183540.3813685-22-mhonap@nvidia.com>
On Thu, Sep 17, 2026 at 12:05:34AM +0800, mhonap@nvidia.com wrote:
> From: Manish Honap <mhonap@nvidia.com>
>
> The HDM decoder register block lives in the component BAR that vfio-pci
> owns. The guest reads the decoder only through the trapped, read-only
> decoder region; it must not reach the physical registers through the BAR
> directly, and a host read of the range through a kernel mapping could
> abort as a fatal host SError.
>
> Add the block to the generic excluded-range list with
> VFIO_PCI_EXCLUDE_MMAP | VFIO_PCI_EXCLUDE_READ | VFIO_PCI_EXCLUDE_WRITE
> similar to the MSI-X exclusion.
>
Hi Manish,
I think we need to block eventfd write and BAR DMA as well ?
Have some comments below.
> Assisted-by: LLM
> Signed-off-by: Manish Honap <mhonap@nvidia.com>
> ---
> drivers/vfio/pci/cxl/vfio_cxl_core.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/vfio/pci/cxl/vfio_cxl_core.c b/drivers/vfio/pci/cxl/vfio_cxl_core.c
> index da04776356e4..37e8a3b54cfb 100644
> --- a/drivers/vfio/pci/cxl/vfio_cxl_core.c
> +++ b/drivers/vfio/pci/cxl/vfio_cxl_core.c
> @@ -435,8 +435,25 @@ static int vfio_cxl_add_region(struct vfio_pci_core_device *vdev, u32 subtype,
> static int vfio_cxl_open_device(struct vfio_pci_core_device *vdev)
> {
> struct vfio_cxl_state *cxl = vdev->cxl;
> + struct pci_dev *pdev = vdev->pdev;
> int ret;
>
> + /*
> + * Keep the HDM decoder block out of the guest's direct BAR access: the
> + * guest reaches it only through the trapped decoder region, and a host
> + * read of the range through a kernel mapping could abort as an SError.
> + * Exclude it from mmap, fill reads with -1 and drop writes. The list is
> + * cleared on close, so re-add it per open.
> + */
> + ret = vfio_pci_core_add_excluded_range(vdev, pdev->hdm->hdm_bar,
> + pdev->hdm->hdm_offset,
> + cxl->hdm_len,
> + VFIO_PCI_EXCLUDE_MMAP |
> + VFIO_PCI_EXCLUDE_READ |
> + VFIO_PCI_EXCLUDE_WRITE);
This adds the HDM reg to the exclusion list, but the eventfd and BAR DMA path doesn't
check that.
Maybe we need to block those 2 path as well ?
Best regards,
Richard Cheng.
> + if (ret)
> + return ret;
> +
> /*
> * vfio_pci_core_disable() frees all dynamic regions on close, so register
> * them here per open rather than at bind. A failed first open never
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2026-09-17 7:28 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-16 18:35 [PATCH v5 00/27] vfio/pci: Add CXL Type-2 device passthrough support mhonap
2026-09-16 18:35 ` [PATCH v5 01/27] cxl/regs: Split the BAR block request and ioremap helpers mhonap
2026-09-16 18:35 ` [PATCH v5 02/27] cxl/regs: Let a BAR-owning driver own the component register block mhonap
2026-09-16 18:35 ` [PATCH v5 03/27] cxl: Move component register defines to uapi/cxl/cxl_regs.h mhonap
2026-09-16 18:35 ` [PATCH v5 04/27] cxl: Add cxl_reset_dvsec_sequence() for vfio-pci mhonap
2026-09-16 18:35 ` [PATCH v5 05/27] vfio/pci: Add the CXL provider ops registration interface mhonap
2026-09-16 18:35 ` [PATCH v5 06/27] vfio/pci: Detect CXL devices and load the CXL provider on demand mhonap
2026-09-17 8:48 ` Richard Cheng
2026-09-16 18:35 ` [PATCH v5 07/27] vfio/pci: Honor -EPROBE_DEFER from CXL provider probe mhonap
2026-09-16 18:35 ` [PATCH v5 08/27] vfio/pci: Fall back to plain vfio-pci when CXL init fails mhonap
2026-09-16 18:35 ` [PATCH v5 09/27] vfio/pci: Add a generic excluded-range list mhonap
2026-09-16 18:35 ` [PATCH v5 10/27] vfio/pci: Migrate MSI-X exclusion onto the " mhonap
2026-09-16 18:35 ` [PATCH v5 11/27] vfio/pci: Virtualize the CXL DVSEC in vfio_pci_config.c mhonap
2026-09-16 18:35 ` [PATCH v5 12/27] vfio/pci: Call the CXL open and close hooks around device use mhonap
2026-09-16 18:35 ` [PATCH v5 13/27] vfio/pci: Bracket PCI resets with the CXL reset hooks mhonap
2026-09-16 18:35 ` [PATCH v5 14/27] vfio/pci: Provide an opt-out for the CXL Type-2 extensions mhonap
2026-09-16 18:35 ` [PATCH v5 15/27] vfio/cxl: Add the vfio-cxl provider module skeleton mhonap
2026-09-16 18:35 ` [PATCH v5 16/27] vfio/cxl: Create the CXL memdev and set media ready at bind mhonap
2026-09-16 18:35 ` [PATCH v5 17/27] vfio/cxl: Own the whole component register BAR mhonap
2026-09-16 18:35 ` [PATCH v5 18/27] vfio/cxl: Expose the HDM memory region to the guest mhonap
2026-09-16 18:35 ` [PATCH v5 19/27] vfio/cxl: Contain HDM memory errors with memory_failure() mhonap
2026-09-16 18:35 ` [PATCH v5 20/27] vfio/cxl: Expose the HDM decoder registers read-only to the guest mhonap
2026-09-16 18:35 ` [PATCH v5 21/27] vfio/cxl: Exclude the HDM decoder registers from direct BAR access mhonap
2026-09-17 7:28 ` Richard Cheng [this message]
2026-09-16 18:35 ` [PATCH v5 22/27] vfio/cxl: Clear the HDM access gate after a hot reset mhonap
2026-09-16 18:35 ` [PATCH v5 23/27] vfio/cxl: Describe the CXL device and decoder geometry to userspace mhonap
2026-09-16 18:35 ` [PATCH v5 24/27] vfio/cxl: Export the HDM memory region as a dma-buf mhonap
2026-09-17 7:55 ` Richard Cheng
2026-09-16 18:35 ` [PATCH v5 25/27] vfio/cxl: Run the CXL reset at the vfio reset points mhonap
2026-09-17 8:11 ` Richard Cheng
2026-09-16 18:35 ` [PATCH v5 26/27] Documentation: vfio-pci: Document CXL Type-2 device passthrough mhonap
2026-09-16 19:33 ` Gregory Price
2026-09-16 18:35 ` [PATCH v5 27/27] selftests/vfio: Add CXL Type-2 passthrough tests mhonap
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