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From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Orgad Shaneh <orgads@gmail.com>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/5] MIPS: OCTEON: read the L2 crippled fuses from MIO_FUS_DAT3 on OCTEON II
Date: Sat, 26 Sep 2026 11:35:09 +0200	[thread overview]
Message-ID: <areRzY9uH3rTScm4@alpha.franken.de> (raw)
In-Reply-To: <20260915071306.15006-3-orgads@gmail.com>

On Tue, Sep 15, 2026 at 07:12:46AM +0000, Orgad Shaneh wrote:
> prom_init() decides whether to lock lines into the L2 by reading
> L2D_FUS3, a CN3XXX/CN5XXX register. On OCTEON II the fuses that cripple
> the L2 are MIO_FUS_DAT3[l2c_crip] - which is what cvmx_l2c_get_num_assoc()
> already reads for those parts - so the test looks at an address that is
> not a register on the chip and gets a meaningless answer: it can skip
> L2 locking on a healthy cache, or lock into a reduced one.
> 
> Pick the register by family in a small helper.
> 
> Assisted-by: Claude:claude-opus-5
> Signed-off-by: Orgad Shaneh <orgads@gmail.com>
> ---
> diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
> --- a/arch/mips/cavium-octeon/setup.c
> +++ b/arch/mips/cavium-octeon/setup.c
> @@ -653,6 +653,24 @@ void octeon_user_io_init(void)
>  	write_c0_derraddr1(0);
>  }
>  
> +#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
> +static bool __init octeon_l2_is_crippled(void)
> +{
> +	/*
> +	 * L2D_FUS3 exists on CN3XXX/CN5XXX only. On OCTEON II the
> +	 * crippled-L2 fuses live in MIO_FUS_DAT3[l2c_crip].
> +	 */
> +	if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
> +		union cvmx_mio_fus_dat3 fus_dat3;
> +
> +		fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
> +		return fus_dat3.s.l2c_crip != 0;
> +	}
> +
> +	return cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34);
> +}
> +#endif
> +
>  /**
>   * prom_init - Early entry point for arch setup
>   */
> @@ -801,7 +819,7 @@ void __init prom_init(void)
>  	}
>  
>  #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
> -	if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
> +	if (octeon_l2_is_crippled()) {
>  		pr_info("Skipping L2 locking due to reduced L2 cache size\n");
>  	} else {
>  		uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
> -- 
> 2.47.0

applied to mips-next

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

  reply	other threads:[~2026-09-26 10:28 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-15  7:12 [PATCH 1/5] MIPS: OCTEON: cvmx-l2c: use the OCTEON II register model on all CN6XXX Orgad Shaneh
2026-09-15  7:12 ` [PATCH 2/5] MIPS: OCTEON: cvmx-l2c: add the CN66XX L2 geometry Orgad Shaneh
2026-09-26  9:34   ` Thomas Bogendoerfer
2026-09-15  7:12 ` [PATCH 3/5] MIPS: OCTEON: read the L2 crippled fuses from MIO_FUS_DAT3 on OCTEON II Orgad Shaneh
2026-09-26  9:35   ` Thomas Bogendoerfer [this message]
2026-09-15  7:12 ` [PATCH 4/5] MIPS: OCTEON: program L2C_CTL, not L2C_CFG, " Orgad Shaneh
2026-09-26  9:35   ` Thomas Bogendoerfer
2026-09-15  7:12 ` [PATCH 5/5] MIPS: OCTEON: require the Core-14449 workaround only on CN63XX pass 1 Orgad Shaneh
2026-09-26  9:35   ` Thomas Bogendoerfer
2026-09-26  9:34 ` [PATCH 1/5] MIPS: OCTEON: cvmx-l2c: use the OCTEON II register model on all CN6XXX Thomas Bogendoerfer

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