* [PATCH v3 1/6] arm64: dts: qcom: nord: Add support for ADSP and CDSPs
2026-09-20 8:49 [PATCH v3 0/6] arm64: dts: qcom: nord: Add remoteproc and PMIC support Shawn Guo
@ 2026-09-20 8:49 ` Shawn Guo
2026-09-21 7:55 ` Abel Vesa
2026-09-20 8:49 ` [PATCH v3 2/6] arm64: dts: qcom: nord-rrd: Enable " Shawn Guo
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Shawn Guo @ 2026-09-20 8:49 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, Dhruvin Rajpura, Anandu Krishnan E,
linux-arm-msm, devicetree, linux-kernel, Shawn Guo,
Konrad Dybcio
Add device tree nodes to support ADSP (HPASS DSP) and CDSPs remoteproc
on Nord SoC.
This includes:
- SMEM memory reservation used by the inter-processor communication
infrastructure
- IPCC mailbox controller for inter-processor signalling
- AOSS QMP node for load state power management
- SMP2P nodes providing stop control and fault/crash interrupt signals
- Remoteproc nodes with a GLINK edge and FastRPC compute contexts for
userspace offload
The embedded variant specific power domains, XO clock, and interconnect
paths are filled in nord-embedded.dtsi.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 63 ++
arch/arm64/boot/dts/qcom/nord-ipcc.h | 144 ++++
arch/arm64/boot/dts/qcom/nord.dtsi | 885 ++++++++++++++++++++
3 files changed, 1092 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/nord-ipcc.h
diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index 568fe68cd185..c7ac2e66632e 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -363,6 +363,69 @@ &qupv3_2 {
"s-ahb";
};
+&remoteproc_adsp {
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ interconnects = <&hpass_ag_noc MASTER_HPASS_PROC_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+};
+
+&remoteproc_cdsp0 {
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ interconnects = <&nsp_data_noc_0 MASTER_NSP0_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_NMXC>,
+ <&rpmhpd RPMHPD_NSP0>;
+ power-domain-names = "cx",
+ "mx",
+ "nsp";
+};
+
+&remoteproc_cdsp1 {
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ interconnects = <&nsp_data_noc_1 MASTER_NSP1_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_NMXC>,
+ <&rpmhpd RPMHPD_NSP1>;
+ power-domain-names = "cx",
+ "mx",
+ "nsp";
+};
+
+&remoteproc_cdsp2 {
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ interconnects = <&nsp_data_noc_2 MASTER_NSP2_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_NMXC>,
+ <&rpmhpd RPMHPD_NSP2>;
+ power-domain-names = "cx",
+ "mx",
+ "nsp";
+};
+
+&remoteproc_cdsp3 {
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ interconnects = <&nsp_data_noc_3 MASTER_NSP3_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_NMXC>,
+ <&rpmhpd RPMHPD_NSP3>;
+ power-domain-names = "cx",
+ "mx",
+ "nsp";
+};
+
&spi0 {
clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
diff --git a/arch/arm64/boot/dts/qcom/nord-ipcc.h b/arch/arm64/boot/dts/qcom/nord-ipcc.h
new file mode 100644
index 000000000000..8bf9b0875b6d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/nord-ipcc.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DTS_NORD_IPCC_H
+#define __DTS_NORD_IPCC_H
+
+/* Physical client IDs */
+#define IPCC_MPROC_AOP 0
+#define IPCC_MPROC_TZ 1
+#define IPCC_MPROC_ADSP0 2
+#define IPCC_MPROC_NSP0 3
+#define IPCC_MPROC_NSP1 4
+#define IPCC_MPROC_NSP2 5
+#define IPCC_MPROC_NSP3 6
+#define IPCC_MPROC_APSS_NS0 7
+#define IPCC_MPROC_APSS_NS1 8
+#define IPCC_MPROC_APSS_NS2 9
+#define IPCC_MPROC_APSS_NS3 10
+#define IPCC_MPROC_ADSP1 11
+#define IPCC_MPROC_ADSP2 12
+#define IPCC_MPROC_APSS_NS4 13
+#define IPCC_MPROC_SOCCP 15
+#define IPCC_MPROC_CPUCP 16
+#define IPCC_MPROC_A78CSS 17
+#define IPCC_MPROC_TMESS 18
+#define IPCC_MPROC_SAIL0 19
+#define IPCC_MPROC_SAIL1 20
+#define IPCC_MPROC_SAIL2 21
+#define IPCC_MPROC_SAIL3 22
+#define IPCC_MPROC_SAIL4 23
+#define IPCC_MPROC_SAIL5 24
+
+#define IPCC_COMPUTE_L0_ADSP0 0
+#define IPCC_COMPUTE_L0_NSP0 1
+#define IPCC_COMPUTE_L0_NSP1 2
+#define IPCC_COMPUTE_L0_NSP2 3
+#define IPCC_COMPUTE_L0_NSP3 4
+#define IPCC_COMPUTE_L0_APSS_NS0 5
+#define IPCC_COMPUTE_L0_GPU0 6
+#define IPCC_COMPUTE_L0_APSS_NS1 7
+#define IPCC_COMPUTE_L0_APSS_NS2 8
+#define IPCC_COMPUTE_L0_APSS_NS3 9
+#define IPCC_COMPUTE_L0_CVP 10
+#define IPCC_COMPUTE_L0_ICP0 11
+#define IPCC_COMPUTE_L0_ICP1 12
+#define IPCC_COMPUTE_L0_VPU 13
+#define IPCC_COMPUTE_L0_DPU0 14
+#define IPCC_COMPUTE_L0_DPU1 15
+#define IPCC_COMPUTE_L0_ADSP1 16
+#define IPCC_COMPUTE_L0_ADSP2 17
+#define IPCC_COMPUTE_L0_APSS_NS4 18
+#define IPCC_COMPUTE_L0_SOCCP 20
+#define IPCC_COMPUTE_L0_SAIL0 21
+#define IPCC_COMPUTE_L0_SAIL1 22
+#define IPCC_COMPUTE_L0_SAIL2 23
+#define IPCC_COMPUTE_L0_SAIL3 24
+#define IPCC_COMPUTE_L0_SAIL4 25
+#define IPCC_COMPUTE_L0_SAIL5 26
+#define IPCC_COMPUTE_L0_IPA 27
+#define IPCC_COMPUTE_L0_GPU1 28
+
+#define IPCC_COMPUTE_L1_ADSP0 0
+#define IPCC_COMPUTE_L1_NSP0 1
+#define IPCC_COMPUTE_L1_NSP1 2
+#define IPCC_COMPUTE_L1_NSP2 3
+#define IPCC_COMPUTE_L1_NSP3 4
+#define IPCC_COMPUTE_L1_APSS_NS0 5
+#define IPCC_COMPUTE_L1_GPU0 6
+#define IPCC_COMPUTE_L1_APSS_NS1 7
+#define IPCC_COMPUTE_L1_APSS_NS2 8
+#define IPCC_COMPUTE_L1_APSS_NS3 9
+#define IPCC_COMPUTE_L1_CVP 10
+#define IPCC_COMPUTE_L1_ICP0 11
+#define IPCC_COMPUTE_L1_ICP1 12
+#define IPCC_COMPUTE_L1_VPU 13
+#define IPCC_COMPUTE_L1_DPU0 14
+#define IPCC_COMPUTE_L1_DPU1 15
+#define IPCC_COMPUTE_L1_ADSP1 16
+#define IPCC_COMPUTE_L1_ADSP2 17
+#define IPCC_COMPUTE_L1_APSS_NS4 18
+#define IPCC_COMPUTE_L1_SOCCP 20
+#define IPCC_COMPUTE_L1_SAIL0 21
+#define IPCC_COMPUTE_L1_SAIL1 22
+#define IPCC_COMPUTE_L1_SAIL2 23
+#define IPCC_COMPUTE_L1_SAIL3 24
+#define IPCC_COMPUTE_L1_SAIL4 25
+#define IPCC_COMPUTE_L1_SAIL5 26
+#define IPCC_COMPUTE_L1_IPA 27
+#define IPCC_COMPUTE_L1_GPU1 28
+
+#define IPCC_PERIPH_ADSP0 0
+#define IPCC_PERIPH_NSP0 1
+#define IPCC_PERIPH_NSP1 2
+#define IPCC_PERIPH_NSP2 3
+#define IPCC_PERIPH_NSP3 4
+#define IPCC_PERIPH_APSS_NS0 5
+#define IPCC_PERIPH_PCIE0 6
+#define IPCC_PERIPH_PCIE1 7
+#define IPCC_PERIPH_APSS_NS1 8
+#define IPCC_PERIPH_APSS_NS2 9
+#define IPCC_PERIPH_APSS_NS3 10
+#define IPCC_PERIPH_ADSP1 11
+#define IPCC_PERIPH_ADSP2 12
+#define IPCC_PERIPH_APSS_NS4 13
+
+#define IPCC_FENCE_ADSP0 0
+#define IPCC_FENCE_NSP0 1
+#define IPCC_FENCE_NSP1 2
+#define IPCC_FENCE_NSP2 3
+#define IPCC_FENCE_NSP3 4
+#define IPCC_FENCE_APSS_NS0 5
+#define IPCC_FENCE_GPU0 6
+#define IPCC_FENCE_APSS_NS1 7
+#define IPCC_FENCE_APSS_NS2 8
+#define IPCC_FENCE_APSS_NS3 9
+#define IPCC_FENCE_CVP 10
+#define IPCC_FENCE_ICP0 11
+#define IPCC_FENCE_ICP1 12
+#define IPCC_FENCE_CAM_ENG0 13
+#define IPCC_FENCE_CAM_ENG1 14
+#define IPCC_FENCE_CAM_ENG2 15
+#define IPCC_FENCE_CAM_ENG3 16
+#define IPCC_FENCE_CAM_ENG4 17
+#define IPCC_FENCE_CAM_ENG5 18
+#define IPCC_FENCE_CAM_ENG6 19
+#define IPCC_FENCE_CAM_ENG7 20
+#define IPCC_FENCE_CAM_ENG8 21
+#define IPCC_FENCE_CAM_ENG9 22
+#define IPCC_FENCE_CAM_ENG10 23
+#define IPCC_FENCE_CAM_ENG11 24
+#define IPCC_FENCE_CAM_ENG12 25
+#define IPCC_FENCE_VPU 26
+#define IPCC_FENCE_DPU0 27
+#define IPCC_FENCE_DPU1 28
+#define IPCC_FENCE_ADSP1 29
+#define IPCC_FENCE_ADSP2 30
+#define IPCC_FENCE_APSS_NS4 31
+#define IPCC_FENCE_SOCCP 33
+#define IPCC_FENCE_IPA 34
+#define IPCC_FENCE_GPU1 35
+
+#endif
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index e0496fd40c30..d413341eac41 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -4,6 +4,9 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+
+#include "nord-ipcc.h"
/ {
interrupt-parent = <&intc>;
@@ -685,6 +688,13 @@ qdss_apps_mem: qdss-apps-region@87b00000 {
no-map;
};
+ smem_mem: smem@89b00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x89b00000 0x0 0x400000>;
+ no-map;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
global_sync_mem: global-sync-region@89f00000 {
reg = <0x0 0x89f00000 0x0 0x400000>;
no-map;
@@ -902,6 +912,117 @@ dump_mem: mem-dump-region {
};
};
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ interrupts-extended = <&ipcc0 IPCC_MPROC_ADSP0
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc0 IPCC_MPROC_ADSP0
+ IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,smem = <443>, <429>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ smp2p_adsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_adsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp0 {
+ compatible = "qcom,smp2p";
+ interrupts-extended = <&ipcc0 IPCC_MPROC_NSP0
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc0 IPCC_MPROC_NSP0 IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,smem = <94>, <432>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ smp2p_cdsp0_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp0_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp1 {
+ compatible = "qcom,smp2p";
+ interrupts-extended = <&ipcc0 IPCC_MPROC_NSP1
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc0 IPCC_MPROC_NSP1 IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,smem = <617>, <616>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <69>;
+
+ smp2p_cdsp1_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp1_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp2 {
+ compatible = "qcom,smp2p";
+ interrupts-extended = <&ipcc0 IPCC_MPROC_NSP2
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc0 IPCC_MPROC_NSP2 IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,smem = <617>, <616>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <133>;
+
+ smp2p_cdsp2_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp2_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp3 {
+ compatible = "qcom,smp2p";
+ interrupts-extended = <&ipcc0 IPCC_MPROC_NSP3
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc0 IPCC_MPROC_NSP3 IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,smem = <617>, <616>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <197>;
+
+ smp2p_cdsp3_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp3_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
@@ -1518,6 +1639,104 @@ tcsr: syscon@1f60000 {
reg = <0x0 0x01f60000 0x0 0xa0000>;
};
+ remoteproc_adsp: remoteproc@4c00000 {
+ compatible = "qcom,nord-adsp-pas";
+ reg = <0x0 0x04c00000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ memory-region = <&hpass_dsp0_mem>,
+ <&hpass_dsp0_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc0 IPCC_MPROC_ADSP0
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc0 IPCC_MPROC_ADSP0
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <2>;
+ label = "adsp";
+
+ fastrpc {
+ compatible = "qcom,nord-fastrpc",
+ "qcom,kaanapali-fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+ memory-region = <&hpass_rpc_remote_heap_mem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu_0 0x09e3 0x0000>,
+ <&apps_smmu_0 0x0a43 0x0020>,
+ <&apps_smmu_0 0x0a63 0x0020>,
+ <&apps_smmu_0 0x0a83 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu_0 0x09e4 0x0000>,
+ <&apps_smmu_0 0x0a44 0x0020>,
+ <&apps_smmu_0 0x0a64 0x0020>,
+ <&apps_smmu_0 0x0a84 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu_0 0x09e5 0x0000>,
+ <&apps_smmu_0 0x0a45 0x0020>,
+ <&apps_smmu_0 0x0a65 0x0020>,
+ <&apps_smmu_0 0x0a85 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu_0 0x09e6 0x0000>,
+ <&apps_smmu_0 0x0a46 0x0020>,
+ <&apps_smmu_0 0x0a66 0x0020>,
+ <&apps_smmu_0 0x0a86 0x0000>;
+ dma-coherent;
+ };
+ };
+ };
+ };
+
+ ipcc0: mailbox@9007000 {
+ compatible = "qcom,nord-ipcc",
+ "qcom,ipcc";
+ reg = <0x0 0x09007000 0x0 0x1000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,nord-pdc",
"qcom,pdc";
@@ -1637,6 +1856,16 @@ tsens7: thermal-sensor@c233000 {
#thermal-sensor-cells = <1>;
};
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,nord-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0x0 0x0c300000 0x0 0x400>;
+ interrupts-extended = <&ipcc0 IPCC_MPROC_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc0 IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ #clock-cells = <0>;
+ };
+
tlmm: pinctrl@f100000 {
compatible = "qcom,nord-tlmm";
reg = <0x0 0x0f100000 0x0 0xc0000>;
@@ -2071,6 +2300,662 @@ watchdog@17826000 {
clocks = <&sleep_clk>;
interrupts = <GIC_ESPI 848 IRQ_TYPE_EDGE_RISING>;
};
+
+ remoteproc_cdsp0: remoteproc@1f300000 {
+ compatible = "qcom,nord-cdsp0-pas";
+ reg = <0x0 0x1f300000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 499 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp0_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ memory-region = <&cdsp0_mem>,
+ <&q6_cdsp0_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_cdsp0_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc0 IPCC_MPROC_NSP0
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc0 IPCC_MPROC_NSP0
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <5>;
+ label = "cdsp";
+
+ fastrpc {
+ compatible = "qcom,nord-fastrpc",
+ "qcom,kaanapali-fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "cdsp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu_2 0x0301 0x0040>,
+ <&apps_smmu_2 0x0341 0x0040>,
+ <&apps_smmu_2 0x0361 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu_2 0x0302 0x0040>,
+ <&apps_smmu_2 0x0342 0x0040>,
+ <&apps_smmu_2 0x0362 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu_2 0x0303 0x0040>,
+ <&apps_smmu_2 0x0343 0x0040>,
+ <&apps_smmu_2 0x0363 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu_2 0x0304 0x0040>,
+ <&apps_smmu_2 0x0344 0x0040>,
+ <&apps_smmu_2 0x0364 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu_2 0x0305 0x0000>,
+ <&apps_smmu_2 0x0345 0x0020>,
+ <&apps_smmu_2 0x0365 0x0020>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu_2 0x0306 0x0040>,
+ <&apps_smmu_2 0x0346 0x0040>,
+ <&apps_smmu_2 0x0366 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu_2 0x0307 0x0040>,
+ <&apps_smmu_2 0x0347 0x0040>,
+ <&apps_smmu_2 0x0367 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&apps_smmu_2 0x0308 0x0040>,
+ <&apps_smmu_2 0x0348 0x0040>,
+ <&apps_smmu_2 0x0368 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&apps_smmu_2 0x0309 0x0040>,
+ <&apps_smmu_2 0x0349 0x0040>,
+ <&apps_smmu_2 0x0369 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@10 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <10>;
+ iommus = <&apps_smmu_2 0x030a 0x0040>,
+ <&apps_smmu_2 0x034a 0x0040>,
+ <&apps_smmu_2 0x036a 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@11 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <11>;
+ iommus = <&apps_smmu_2 0x030b 0x0040>,
+ <&apps_smmu_2 0x034b 0x0040>,
+ <&apps_smmu_2 0x036b 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+ iommus = <&apps_smmu_2 0x030c 0x0040>,
+ <&apps_smmu_2 0x034c 0x0040>,
+ <&apps_smmu_2 0x036c 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@13 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <13>;
+ iommus = <&apps_smmu_2 0x030d 0x0000>,
+ <&apps_smmu_2 0x034d 0x0020>,
+ <&apps_smmu_2 0x036d 0x0020>;
+ dma-coherent;
+ };
+ };
+ };
+ };
+
+ remoteproc_cdsp1: remoteproc@1f700000 {
+ compatible = "qcom,nord-cdsp1-pas";
+ reg = <0x0 0x1f700000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 500 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp1_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ memory-region = <&cdsp1_mem>,
+ <&q6_cdsp1_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_cdsp1_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc0 IPCC_MPROC_NSP1
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc0 IPCC_MPROC_NSP1
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <69>;
+ label = "cdsp";
+
+ fastrpc {
+ compatible = "qcom,nord-fastrpc",
+ "qcom,kaanapali-fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "cdsp1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu_2 0x0701 0x0040>,
+ <&apps_smmu_2 0x0741 0x0040>,
+ <&apps_smmu_2 0x0761 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu_2 0x0702 0x0040>,
+ <&apps_smmu_2 0x0742 0x0040>,
+ <&apps_smmu_2 0x0762 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu_2 0x0703 0x0040>,
+ <&apps_smmu_2 0x0743 0x0040>,
+ <&apps_smmu_2 0x0763 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu_2 0x0704 0x0040>,
+ <&apps_smmu_2 0x0744 0x0040>,
+ <&apps_smmu_2 0x0764 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu_2 0x0705 0x0000>,
+ <&apps_smmu_2 0x0745 0x0020>,
+ <&apps_smmu_2 0x0765 0x0020>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu_2 0x0706 0x0040>,
+ <&apps_smmu_2 0x0746 0x0040>,
+ <&apps_smmu_2 0x0766 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu_2 0x0707 0x0040>,
+ <&apps_smmu_2 0x0747 0x0040>,
+ <&apps_smmu_2 0x0767 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&apps_smmu_2 0x0708 0x0040>,
+ <&apps_smmu_2 0x0748 0x0040>,
+ <&apps_smmu_2 0x0768 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&apps_smmu_2 0x0709 0x0040>,
+ <&apps_smmu_2 0x0749 0x0040>,
+ <&apps_smmu_2 0x0769 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@10 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <10>;
+ iommus = <&apps_smmu_2 0x070a 0x0040>,
+ <&apps_smmu_2 0x074a 0x0040>,
+ <&apps_smmu_2 0x076a 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@11 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <11>;
+ iommus = <&apps_smmu_2 0x070b 0x0040>,
+ <&apps_smmu_2 0x074b 0x0040>,
+ <&apps_smmu_2 0x076b 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+ iommus = <&apps_smmu_2 0x070c 0x0040>,
+ <&apps_smmu_2 0x074c 0x0040>,
+ <&apps_smmu_2 0x076c 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@13 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <13>;
+ iommus = <&apps_smmu_2 0x070d 0x0000>,
+ <&apps_smmu_2 0x074d 0x0020>,
+ <&apps_smmu_2 0x076d 0x0020>;
+ dma-coherent;
+ };
+ };
+ };
+ };
+
+ remoteproc_cdsp2: remoteproc@1fb00000 {
+ compatible = "qcom,nord-cdsp2-pas";
+ reg = <0x0 0x1fb00000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 501 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp2_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp2_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp2_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp2_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp2_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ memory-region = <&cdsp2_mem>,
+ <&q6_cdsp2_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_cdsp2_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc0 IPCC_MPROC_NSP2
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc0 IPCC_MPROC_NSP2
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <133>;
+ label = "cdsp";
+
+ fastrpc {
+ compatible = "qcom,nord-fastrpc",
+ "qcom,kaanapali-fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "cdsp2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu_2 0x0b01 0x0040>,
+ <&apps_smmu_2 0x0b41 0x0040>,
+ <&apps_smmu_2 0x0b61 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu_2 0x0b02 0x0040>,
+ <&apps_smmu_2 0x0b42 0x0040>,
+ <&apps_smmu_2 0x0b62 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu_2 0x0b03 0x0040>,
+ <&apps_smmu_2 0x0b43 0x0040>,
+ <&apps_smmu_2 0x0b63 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu_2 0x0b04 0x0040>,
+ <&apps_smmu_2 0x0b44 0x0040>,
+ <&apps_smmu_2 0x0b64 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu_2 0x0b05 0x0000>,
+ <&apps_smmu_2 0x0b45 0x0020>,
+ <&apps_smmu_2 0x0b65 0x0020>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu_2 0x0b06 0x0040>,
+ <&apps_smmu_2 0x0b46 0x0040>,
+ <&apps_smmu_2 0x0b66 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu_2 0x0b07 0x0040>,
+ <&apps_smmu_2 0x0b47 0x0040>,
+ <&apps_smmu_2 0x0b67 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&apps_smmu_2 0x0b08 0x0040>,
+ <&apps_smmu_2 0x0b48 0x0040>,
+ <&apps_smmu_2 0x0b68 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&apps_smmu_2 0x0b09 0x0040>,
+ <&apps_smmu_2 0x0b49 0x0040>,
+ <&apps_smmu_2 0x0b69 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@10 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <10>;
+ iommus = <&apps_smmu_2 0x0b0a 0x0040>,
+ <&apps_smmu_2 0x0b4a 0x0040>,
+ <&apps_smmu_2 0x0b6a 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@11 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <11>;
+ iommus = <&apps_smmu_2 0x0b0b 0x0040>,
+ <&apps_smmu_2 0x0b4b 0x0040>,
+ <&apps_smmu_2 0x0b6b 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+ iommus = <&apps_smmu_2 0x0b0c 0x0040>,
+ <&apps_smmu_2 0x0b4c 0x0040>,
+ <&apps_smmu_2 0x0b6c 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@13 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <13>;
+ iommus = <&apps_smmu_2 0x0b0d 0x0000>,
+ <&apps_smmu_2 0x0b4d 0x0020>,
+ <&apps_smmu_2 0x0b6d 0x0020>;
+ dma-coherent;
+ };
+ };
+ };
+ };
+
+ remoteproc_cdsp3: remoteproc@1ff00000 {
+ compatible = "qcom,nord-cdsp3-pas";
+ reg = <0x0 0x1ff00000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 505 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp3_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp3_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp3_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp3_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp3_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ memory-region = <&cdsp3_mem>,
+ <&q6_cdsp3_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_cdsp3_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc0 IPCC_MPROC_NSP3
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc0 IPCC_MPROC_NSP3
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <197>;
+ label = "cdsp";
+
+ fastrpc {
+ compatible = "qcom,nord-fastrpc",
+ "qcom,kaanapali-fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "cdsp3";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu_2 0x0f01 0x0040>,
+ <&apps_smmu_2 0x0f41 0x0040>,
+ <&apps_smmu_2 0x0f61 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu_2 0x0f02 0x0040>,
+ <&apps_smmu_2 0x0f42 0x0040>,
+ <&apps_smmu_2 0x0f62 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu_2 0x0f03 0x0040>,
+ <&apps_smmu_2 0x0f43 0x0040>,
+ <&apps_smmu_2 0x0f63 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu_2 0x0f04 0x0040>,
+ <&apps_smmu_2 0x0f44 0x0040>,
+ <&apps_smmu_2 0x0f64 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu_2 0x0f05 0x0000>,
+ <&apps_smmu_2 0x0f45 0x0020>,
+ <&apps_smmu_2 0x0f65 0x0020>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu_2 0x0f06 0x0040>,
+ <&apps_smmu_2 0x0f46 0x0040>,
+ <&apps_smmu_2 0x0f66 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu_2 0x0f07 0x0040>,
+ <&apps_smmu_2 0x0f47 0x0040>,
+ <&apps_smmu_2 0x0f67 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&apps_smmu_2 0x0f08 0x0040>,
+ <&apps_smmu_2 0x0f48 0x0040>,
+ <&apps_smmu_2 0x0f68 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&apps_smmu_2 0x0f09 0x0040>,
+ <&apps_smmu_2 0x0f49 0x0040>,
+ <&apps_smmu_2 0x0f69 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@10 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <10>;
+ iommus = <&apps_smmu_2 0x0f0a 0x0040>,
+ <&apps_smmu_2 0x0f4a 0x0040>,
+ <&apps_smmu_2 0x0f6a 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@11 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <11>;
+ iommus = <&apps_smmu_2 0x0f0b 0x0040>,
+ <&apps_smmu_2 0x0f4b 0x0040>,
+ <&apps_smmu_2 0x0f6b 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+ iommus = <&apps_smmu_2 0x0f0c 0x0040>,
+ <&apps_smmu_2 0x0f4c 0x0040>,
+ <&apps_smmu_2 0x0f6c 0x0000>;
+ dma-coherent;
+ };
+
+ compute-cb@13 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <13>;
+ iommus = <&apps_smmu_2 0x0f0d 0x0000>,
+ <&apps_smmu_2 0x0f4d 0x0020>,
+ <&apps_smmu_2 0x0f6d 0x0020>;
+ dma-coherent;
+ };
+ };
+ };
+ };
};
arch_timer: timer {
--
2.43.0
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v3 4/6] arm64: dts: qcom: nord: Add PMAU0102 and PMM8650AU PMIC support
2026-09-20 8:49 [PATCH v3 0/6] arm64: dts: qcom: nord: Add remoteproc and PMIC support Shawn Guo
` (2 preceding siblings ...)
2026-09-20 8:49 ` [PATCH v3 3/6] arm64: dts: qcom: nord: Add the SPMI PMIC arbiter Shawn Guo
@ 2026-09-20 8:49 ` Shawn Guo
2026-09-21 8:06 ` Abel Vesa
2026-09-20 8:49 ` [PATCH v3 5/6] dt-bindings: arm: qcom: Document Nord Ride Embedded board Shawn Guo
` (2 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Shawn Guo @ 2026-09-20 8:49 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, Dhruvin Rajpura, Anandu Krishnan E,
linux-arm-msm, devicetree, linux-kernel, Dhruvin Rajpura,
Konrad Dybcio, Shawn Guo
From: Dhruvin Rajpura <drajpura@qti.qualcomm.com>
The Nord platform is supplied by two families of PMICs on the SPMI bus:
eight PMAU0102 devices on USIDs 4 to 11, and one PMM8650AU on USID 0.
Add one dtsi per PMIC type, following the established one-file-per-PMIC
convention, and include both of them from nord-rrd.dts.
The eight PMAU0102 instances are labelled pmau0102_e through pmau0102_l
after their board designators. Each one provides a GPIO controller, an
ADC, and an MBG (Master Bandgap) temperature monitor that reads its die
temperature through a DIE_TEMP ADC channel. The monitors use the
qcom,pmau0102-mbg-tm compatible with qcom,pm8775-mbg-tm as fallback, and
each is hooked up to a thermal zone.
PMM8650AU is the same die as PMM8654AU, so pmm8650au_a reuses the
existing pmm8654au ompatibles while the file is named after the part
actually populated on the board. It provides PON with a power key,
a RTC, and a GPIO controller. The resin is described but left disabled,
for boards that wire it up to enable.
Signed-off-by: Dhruvin Rajpura <drajpura@qti.qualcomm.com>
Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord-rrd.dts | 2 +
arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi | 543 +++++++++++++++++++
arch/arm64/boot/dts/qcom/pmm8650au-nord.dtsi | 54 ++
3 files changed, 599 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/pmm8650au-nord.dtsi
diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qcom/nord-rrd.dts
index e4c3aee441c2..c547963371b4 100644
--- a/arch/arm64/boot/dts/qcom/nord-rrd.dts
+++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts
@@ -9,6 +9,8 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "nord-embedded.dtsi"
+#include "pmau0102-nord.dtsi"
+#include "pmm8650au-nord.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IQ10 RRD";
diff --git a/arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi b/arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi
new file mode 100644
index 000000000000..47ea145f4abb
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi
@@ -0,0 +1,543 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+#include "qcom-adc5-gen3.h"
+
+&spmi_bus {
+ pmau0102_e: pmic@4 {
+ compatible = "qcom,pmau0102", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmau0102_e_mbg_temp: temperature-sensor@d700 {
+ compatible = "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm";
+ reg = <0xd700>;
+ interrupts-extended = <&spmi_bus 0x4 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pmau0102_e_adc ADC5_GEN3_DIE_TEMP(4)>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmau0102_e_adc: adc@7200 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x7200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&spmi_bus 0x4 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@400 {
+ reg = <ADC5_GEN3_REF_GND(4)>;
+ label = "pmau0102_e_ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@401 {
+ reg = <ADC5_GEN3_1P25VREF(4)>;
+ label = "pmau0102_e_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@403 {
+ reg = <ADC5_GEN3_DIE_TEMP(4)>;
+ label = "pmau0102_e_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pmau0102_e_gpios: gpio@8800 {
+ compatible = "qcom,pmau0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmau0102_e_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmau0102_f: pmic@5 {
+ compatible = "qcom,pmau0102", "qcom,spmi-pmic";
+ reg = <0x5 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmau0102_f_mbg_temp: temperature-sensor@d700 {
+ compatible = "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm";
+ reg = <0xd700>;
+ interrupts-extended = <&spmi_bus 0x5 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pmau0102_f_adc ADC5_GEN3_DIE_TEMP(5)>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmau0102_f_adc: adc@7200 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x7200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&spmi_bus 0x5 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@500 {
+ reg = <ADC5_GEN3_REF_GND(5)>;
+ label = "pmau0102_f_ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@501 {
+ reg = <ADC5_GEN3_1P25VREF(5)>;
+ label = "pmau0102_f_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@503 {
+ reg = <ADC5_GEN3_DIE_TEMP(5)>;
+ label = "pmau0102_f_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pmau0102_f_gpios: gpio@8800 {
+ compatible = "qcom,pmau0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmau0102_f_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmau0102_g: pmic@6 {
+ compatible = "qcom,pmau0102", "qcom,spmi-pmic";
+ reg = <0x6 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmau0102_g_mbg_temp: temperature-sensor@d700 {
+ compatible = "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm";
+ reg = <0xd700>;
+ interrupts-extended = <&spmi_bus 0x6 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pmau0102_g_adc ADC5_GEN3_DIE_TEMP(6)>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmau0102_g_adc: adc@7200 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x7200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&spmi_bus 0x6 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@600 {
+ reg = <ADC5_GEN3_REF_GND(6)>;
+ label = "pmau0102_g_ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@601 {
+ reg = <ADC5_GEN3_1P25VREF(6)>;
+ label = "pmau0102_g_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@603 {
+ reg = <ADC5_GEN3_DIE_TEMP(6)>;
+ label = "pmau0102_g_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pmau0102_g_gpios: gpio@8800 {
+ compatible = "qcom,pmau0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmau0102_g_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmau0102_h: pmic@7 {
+ compatible = "qcom,pmau0102", "qcom,spmi-pmic";
+ reg = <0x7 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmau0102_h_mbg_temp: temperature-sensor@d700 {
+ compatible = "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm";
+ reg = <0xd700>;
+ interrupts-extended = <&spmi_bus 0x7 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pmau0102_h_adc ADC5_GEN3_DIE_TEMP(7)>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmau0102_h_adc: adc@7200 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x7200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&spmi_bus 0x7 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@700 {
+ reg = <ADC5_GEN3_REF_GND(7)>;
+ label = "pmau0102_h_ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@701 {
+ reg = <ADC5_GEN3_1P25VREF(7)>;
+ label = "pmau0102_h_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@703 {
+ reg = <ADC5_GEN3_DIE_TEMP(7)>;
+ label = "pmau0102_h_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pmau0102_h_gpios: gpio@8800 {
+ compatible = "qcom,pmau0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmau0102_h_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmau0102_i: pmic@8 {
+ compatible = "qcom,pmau0102", "qcom,spmi-pmic";
+ reg = <0x8 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmau0102_i_mbg_temp: temperature-sensor@d700 {
+ compatible = "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm";
+ reg = <0xd700>;
+ interrupts-extended = <&spmi_bus 0x8 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pmau0102_i_adc ADC5_GEN3_DIE_TEMP(8)>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmau0102_i_adc: adc@7200 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x7200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&spmi_bus 0x8 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@800 {
+ reg = <ADC5_GEN3_REF_GND(8)>;
+ label = "pmau0102_i_ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@801 {
+ reg = <ADC5_GEN3_1P25VREF(8)>;
+ label = "pmau0102_i_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@803 {
+ reg = <ADC5_GEN3_DIE_TEMP(8)>;
+ label = "pmau0102_i_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pmau0102_i_gpios: gpio@8800 {
+ compatible = "qcom,pmau0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmau0102_i_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmau0102_j: pmic@9 {
+ compatible = "qcom,pmau0102", "qcom,spmi-pmic";
+ reg = <0x9 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmau0102_j_mbg_temp: temperature-sensor@d700 {
+ compatible = "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm";
+ reg = <0xd700>;
+ interrupts-extended = <&spmi_bus 0x9 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pmau0102_j_adc ADC5_GEN3_DIE_TEMP(9)>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmau0102_j_adc: adc@7200 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x7200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&spmi_bus 0x9 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@900 {
+ reg = <ADC5_GEN3_REF_GND(9)>;
+ label = "pmau0102_j_ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@901 {
+ reg = <ADC5_GEN3_1P25VREF(9)>;
+ label = "pmau0102_j_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@903 {
+ reg = <ADC5_GEN3_DIE_TEMP(9)>;
+ label = "pmau0102_j_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pmau0102_j_gpios: gpio@8800 {
+ compatible = "qcom,pmau0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmau0102_j_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmau0102_k: pmic@a {
+ compatible = "qcom,pmau0102", "qcom,spmi-pmic";
+ reg = <0xa SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmau0102_k_mbg_temp: temperature-sensor@d700 {
+ compatible = "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm";
+ reg = <0xd700>;
+ interrupts-extended = <&spmi_bus 0xa 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pmau0102_k_adc ADC5_GEN3_DIE_TEMP(0xa)>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmau0102_k_adc: adc@7200 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x7200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&spmi_bus 0xa 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@a00 {
+ reg = <ADC5_GEN3_REF_GND(0xa)>;
+ label = "pmau0102_k_ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@a01 {
+ reg = <ADC5_GEN3_1P25VREF(0xa)>;
+ label = "pmau0102_k_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@a03 {
+ reg = <ADC5_GEN3_DIE_TEMP(0xa)>;
+ label = "pmau0102_k_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pmau0102_k_gpios: gpio@8800 {
+ compatible = "qcom,pmau0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmau0102_k_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmau0102_l: pmic@b {
+ compatible = "qcom,pmau0102", "qcom,spmi-pmic";
+ reg = <0xb SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmau0102_l_mbg_temp: temperature-sensor@d700 {
+ compatible = "qcom,pmau0102-mbg-tm", "qcom,pm8775-mbg-tm";
+ reg = <0xd700>;
+ interrupts-extended = <&spmi_bus 0xb 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pmau0102_l_adc ADC5_GEN3_DIE_TEMP(0xb)>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmau0102_l_adc: adc@7200 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x7200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&spmi_bus 0xb 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@b00 {
+ reg = <ADC5_GEN3_REF_GND(0xb)>;
+ label = "pmau0102_l_ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@b01 {
+ reg = <ADC5_GEN3_1P25VREF(0xb)>;
+ label = "pmau0102_l_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@b03 {
+ reg = <ADC5_GEN3_DIE_TEMP(0xb)>;
+ label = "pmau0102_l_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pmau0102_l_gpios: gpio@8800 {
+ compatible = "qcom,pmau0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmau0102_l_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+/ {
+ thermal-zones {
+ pmau0102_e_thermal: pmau0102-e-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmau0102_e_mbg_temp>;
+
+ trips {
+ trip0 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmau0102_f_thermal: pmau0102-f-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmau0102_f_mbg_temp>;
+
+ trips {
+ trip0 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmau0102_g_thermal: pmau0102-g-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmau0102_g_mbg_temp>;
+
+ trips {
+ trip0 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmau0102_h_thermal: pmau0102-h-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmau0102_h_mbg_temp>;
+
+ trips {
+ trip0 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmau0102_i_thermal: pmau0102-i-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmau0102_i_mbg_temp>;
+
+ trips {
+ trip0 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmau0102_j_thermal: pmau0102-j-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmau0102_j_mbg_temp>;
+
+ trips {
+ trip0 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmau0102_k_thermal: pmau0102-k-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmau0102_k_mbg_temp>;
+
+ trips {
+ trip0 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmau0102_l_thermal: pmau0102-l-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmau0102_l_mbg_temp>;
+
+ trips {
+ trip0 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pmm8650au-nord.dtsi b/arch/arm64/boot/dts/qcom/pmm8650au-nord.dtsi
new file mode 100644
index 000000000000..1282e5bae591
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmm8650au-nord.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pmm8650au_a: pmic@0 {
+ compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmm8650au_a_pon: pon@1200 {
+ compatible = "qcom,pmm8654au-pon", "qcom,pmk8350-pon";
+ reg = <0x1200>, <0x800>;
+ reg-names = "hlos", "pbs";
+
+ pmm8650au_a_pon_pwrkey: pwrkey {
+ compatible = "qcom,pmm8654au-pwrkey", "qcom,pmk8350-pwrkey";
+ interrupts-extended = <&spmi_bus 0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_POWER>;
+ debounce = <15625>;
+ };
+
+ pmm8650au_a_pon_resin: resin {
+ compatible = "qcom,pmm8654au-resin", "qcom,pmk8350-resin";
+ interrupts-extended = <&spmi_bus 0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ status = "disabled";
+ };
+ };
+
+ pmm8650au_a_rtc: rtc@6100 {
+ compatible = "qcom,pmm8654au-rtc", "qcom,pmk8350-rtc";
+ reg = <0x6100>, <0x6200>;
+ reg-names = "rtc", "alarm";
+ interrupts-extended = <&spmi_bus 0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmm8650au_a_gpios: gpio@8800 {
+ compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmm8650au_a_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
--
2.43.0
^ permalink raw reply [flat|nested] 13+ messages in thread