* [PATCH] riscv: fix RVG_SYSTEM_CSR_MASK width mask
@ 2026-09-11 19:42 Aurelien Jarno
2026-10-04 3:44 ` Jisheng Zhang
0 siblings, 1 reply; 2+ messages in thread
From: Aurelien Jarno @ 2026-09-11 19:42 UTC (permalink / raw)
To: linux-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Andy Chiu, Conor Dooley,
open list:RISC-V ARCHITECTURE
Cc: Aurelien Jarno
RVG_SYSTEM_CSR_MASK should be 12 bits [31:20], shifted down by 20 bits.
Replace GENMASK(12, 0) by GENMASK(11, 0).
Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
arch/riscv/include/asm/insn.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index c3005573e8c9..ad348d8b8857 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -142,7 +142,7 @@
#define RVG_OPCODE_JAL 0x6f
#define RVG_OPCODE_SYSTEM 0x73
#define RVG_SYSTEM_CSR_OFF 20
-#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0)
+#define RVG_SYSTEM_CSR_MASK GENMASK(11, 0)
/* parts of opcode for RVF, RVD and RVQ */
#define RVFDQ_FL_FS_WIDTH_OFF 12
--
2.53.0
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] riscv: fix RVG_SYSTEM_CSR_MASK width mask
2026-09-11 19:42 [PATCH] riscv: fix RVG_SYSTEM_CSR_MASK width mask Aurelien Jarno
@ 2026-10-04 3:44 ` Jisheng Zhang
0 siblings, 0 replies; 2+ messages in thread
From: Jisheng Zhang @ 2026-10-04 3:44 UTC (permalink / raw)
To: Aurelien Jarno
Cc: linux-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Andy Chiu, Conor Dooley,
open list:RISC-V ARCHITECTURE
On Fri, Sep 11, 2026 at 09:42:33PM +0200, Aurelien Jarno wrote:
> RVG_SYSTEM_CSR_MASK should be 12 bits [31:20], shifted down by 20 bits.
> Replace GENMASK(12, 0) by GENMASK(11, 0).
>
> Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/include/asm/insn.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
> index c3005573e8c9..ad348d8b8857 100644
> --- a/arch/riscv/include/asm/insn.h
> +++ b/arch/riscv/include/asm/insn.h
> @@ -142,7 +142,7 @@
> #define RVG_OPCODE_JAL 0x6f
> #define RVG_OPCODE_SYSTEM 0x73
> #define RVG_SYSTEM_CSR_OFF 20
> -#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0)
> +#define RVG_SYSTEM_CSR_MASK GENMASK(11, 0)
>
> /* parts of opcode for RVF, RVD and RVQ */
> #define RVFDQ_FL_FS_WIDTH_OFF 12
> --
> 2.53.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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2026-09-11 19:42 [PATCH] riscv: fix RVG_SYSTEM_CSR_MASK width mask Aurelien Jarno
2026-10-04 3:44 ` Jisheng Zhang
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