[PATCH RESEND v2 0/2] Macro Ordering and Typo Correction

[PATCH RESEND v2 0/2] Macro Ordering and Typo Correction

[Devendra K Verma]

These are minor and cosmetic changes.

o If the macros declaring the bit positions of a register
  are in order then it provides a good view. Corrected
  the ordering for once such register.
o Corrected the typo under the IP related data struct to
  have the correct name under respective IP structs.

Previous reviewed-by tags were part of the following
review:

https://lore.kernel.org/all/aoW7vxy2lpXEbmRq@SMW015318/
https://lore.kernel.org/all/dx5jvko7ygrqugzkt3k74l3d7lk7iauikmxrzuhvn2b4bdv5ub@s2l6zl3alx3z/#t

Devendra K Verma (2):
  dmaengine: dw-edma: Sort Register Field Macros by Bit Position
  dmaengine: dw-edma: correct IP name in xilinx_cpm6_dma_data comment

 drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
2.43.0

[PATCH RESEND v2 1/2] dmaengine: dw-edma: Sort Register Field Macros by Bit Position

[Devendra K Verma]

Sort register field macros by bit position to improve readability.
No functional change.

Signed-off-by: Devendra K Verma <devverma@amd.com>
---
 drivers/dma/dw-edma/dw-edma-pcie.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
index 9f237ba916de..006dea7d6322 100644
--- a/drivers/dma/dw-edma/dw-edma-pcie.c
+++ b/drivers/dma/dw-edma/dw-edma-pcie.c
@@ -31,8 +31,8 @@
 
 #define DW_PCIE_XILINX_MDB_VSEC_DMA_ID		0x6
 #define DW_PCIE_XILINX_MDB_VSEC_ID		0x20
-#define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR		GENMASK(10, 8)
 #define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP		GENMASK(2, 0)
+#define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR		GENMASK(10, 8)
 #define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH	GENMASK(9, 0)
 #define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH	GENMASK(25, 16)
 
-- 
2.43.0

[PATCH RESEND v2 2/2] dmaengine: dw-edma: correct IP name in xilinx_cpm6_dma_data comment

[Devendra K Verma]

Replace 'MDB' with 'CPM6' in the xilinx_cpm6_dma_data comment to
fix the IP name typo.
No functional change.

Signed-off-by: Devendra K Verma <devverma@amd.com>
---
 drivers/dma/dw-edma/dw-edma-pcie.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
index 006dea7d6322..762a693ab55b 100644
--- a/drivers/dma/dw-edma/dw-edma-pcie.c
+++ b/drivers/dma/dw-edma/dw-edma-pcie.c
@@ -146,7 +146,7 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = {
 };
 
 static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = {
-	/* MDB registers location */
+	/* CPM6 registers location */
 	.rg.bar				= BAR_0,
 	.rg.off				= SZ_4K,	/*  4 Kbytes */
 	.rg.sz				= SZ_8K,	/*  8 Kbytes */
-- 
2.43.0

Re: [PATCH RESEND v2 0/2] Macro Ordering and Typo Correction

[Vinod Koul]

On 07-10-26, 15:33, Devendra K Verma wrote:
> These are minor and cosmetic changes.
> 
> o If the macros declaring the bit positions of a register
>   are in order then it provides a good view. Corrected
>   the ordering for once such register.
> o Corrected the typo under the IP related data struct to
>   have the correct name under respective IP structs.
> 
> Previous reviewed-by tags were part of the following
> review:

Please post a v3 after rebase on dma/next. As I told you code has
changed and this does not apply and you posted the same thing again!

> 
> https://lore.kernel.org/all/aoW7vxy2lpXEbmRq@SMW015318/
> https://lore.kernel.org/all/dx5jvko7ygrqugzkt3k74l3d7lk7iauikmxrzuhvn2b4bdv5ub@s2l6zl3alx3z/#t
> 
> Devendra K Verma (2):
>   dmaengine: dw-edma: Sort Register Field Macros by Bit Position
>   dmaengine: dw-edma: correct IP name in xilinx_cpm6_dma_data comment
> 
>  drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> -- 
> 2.43.0

-- 
~Vinod