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From: Andy Shevchenko <andriy.shevchenko@intel.com>
To: Victor Chernyakin <chernyakin.victor.j@outlook.com>
Cc: andy@kernel.org, dlechner@baylibre.com, jic23@kernel.org,
	linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org,
	nuno.sa@analog.com
Subject: Re: [PATCH v2 3/3] iio: cdc: add Texas Instruments FDC1004 driver
Date: Mon, 26 Oct 2026 21:48:17 +0200	[thread overview]
Message-ID: <at-ugcvhOmPFpJP6@ashevche-desk.local> (raw)
In-Reply-To: <SN1PR12MB25284A3A9B89F3CC50689527A5612@SN1PR12MB2528.namprd12.prod.outlook.com>

On Mon, Oct 26, 2026 at 12:06:36PM -0500, Victor Chernyakin wrote:

> > > regmap gives us the two 16-bit registers in native CPU endianness.
> > 
> > It's only if you specify endianess for the whole communication of regmap.
> > I'm too lazy now to check the original patch, but if it's not specified,
> > it means the device native endianess, whatever it is on per register basis.
> 
> We do specify it, yes (the chip is big-endian).
> 
> > > If the CPU is little endian, that means the overall 32 bits aren't in
> > > __be32 format (because the two bytes in each of the halves are swapped).
> > 
> > But yes, even if you do it in the device native endianess, it will still be
> > a pair of 16-bit values with the halves being swapped in case of treating
> > them as a single 32-bit value. This is unfortunate... So, basically this
> > needs to be elaborated in the comment above (where you refer datasheet).
> 
> Can you clarify what you want elaborated? (or are you saying, *if* we
> were working in the device's native endianness, *then* we would have to
> explain that in the comment?)

In the comment you can add something like "We may not read these
two registers in a bulk transfer because they are 16-bit wide and
the byte order in the compound 32-bit value will be wrong."

Yeah, we can address that by swapping 16-bit parts, but it might
make code worse to read (and possibly affect generation as well).
(FWIW, we have even swahw32() for that.)

...

> > What I meant is to compare decomposed val64 as well.
> 
> Hmm, if we only worked with the decomposed values, I think we would have to
> write something like this, which is probably even worse...
> 
>     if ((val < fdc1004_calibscale[0][0]) || 
>         (val == fdc1004_calibscale[0][0] && val2 < fdc1004_calibscale[0][1]) ||
>         (val > fdc1004_calibscale[2][0]) || 
>         (val == fdc1004_calibscale[2][0] && val2 > fdc1004_calibscale[2][1]))
>         return -EINVAL;

It can be avoided by using a helper to validate. Also the meaning of the outer
and inner indices is clearer. With one-dimension array it's unclear what those
indices mean. Ideally the outer indices should match something with datasheet
and in some cases can even be named.

-- 
With Best Regards,
Andy Shevchenko



  reply	other threads:[~2026-10-26 19:48 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-25  5:48 [PATCH v2 0/3] " Victor Chernyakin
2026-10-25  5:48 ` [PATCH v2 1/3] iio: add IIO_VAL_DECIMAL64_{ATTO,ZEPTO,YOCTO} formats Victor Chernyakin
2026-10-25 19:41   ` Andy Shevchenko
2026-10-25  5:48 ` [PATCH v2 2/3] dt-bindings: iio: cdc: add Texas Instruments FDC1004 Victor Chernyakin
2026-10-26 13:04   ` Krzysztof Kozlowski
2026-10-25  5:48 ` [PATCH v2 3/3] iio: cdc: add Texas Instruments FDC1004 driver Victor Chernyakin
2026-10-25 21:24   ` Andy Shevchenko
2026-10-25 20:47 ` [PATCH v2 0/3] " Andy Shevchenko
2026-10-25 21:35   ` Victor Chernyakin
2026-10-26  9:35     ` Andy Shevchenko
2026-10-26 16:57       ` Victor Chernyakin
2026-10-25 22:26   ` [PATCH v2 3/3] " Victor Chernyakin
2026-10-26  9:43     ` Andy Shevchenko
2026-10-26 17:06       ` Victor Chernyakin
2026-10-26 19:48         ` Andy Shevchenko [this message]
2026-10-25 22:39 ` [PATCH v2 0/3] " Jonathan Cameron

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