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From: Andy Shevchenko <andriy.shevchenko@intel.com>
To: Victor Chernyakin <chernyakin.victor.j@outlook.com>
Cc: andy@kernel.org, dlechner@baylibre.com, jic23@kernel.org,
	linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org,
	nuno.sa@analog.com
Subject: Re: [PATCH v2 3/3] iio: cdc: add Texas Instruments FDC1004 driver
Date: Mon, 26 Oct 2026 11:43:55 +0200	[thread overview]
Message-ID: <at8g26_l5JVbqs2i@ashevche-desk.local> (raw)
In-Reply-To: <SN1PR12MB252873B804429C58E090C563A5622@SN1PR12MB2528.namprd12.prod.outlook.com>

On Sun, Oct 25, 2026 at 05:26:37PM -0500, Victor Chernyakin wrote:

...

> > > +/*
> > > + * OFFSET_CAL_CINn: 16 bits, signed. Format: IIO_VAL_DECIMAL64_FEMTO.
> > > + * 1 step = 1/(2^11) pF = 1/(1000 * 2^11) nF = 0.000000488281250 nF.
> > > + */
> > > +static const s64 fdc1004_calibbias[] = {
> > > +	-0x8000 * 488281250UL, /* min */
> > > +	+0x0001 * 488281250UL, /* step */
> > > +	+0x7FFF * 488281250UL, /* max */
> > > +};
> > 
> > Can you explain the negative capacitance meaning? Does it mean some vector
> > (direction) in the physical world?
> 
> If a channel has a parasitic capacitance C, we can set a bias of -C to
> get rid of it.

I see, please add it into the comment above, so nobody will be surprised by
the values which we learnt should never be negative.

...

> > > +		/* The datasheet says to read MSB first, LSB second. */
> > > +		ret = regmap_bulk_read(data->regmap, FDC1004_REG_MEASn_MSB(0),
> > > +				       reg_vals, ARRAY_SIZE(reg_vals));
> > > +		if (ret)
> > > +			return ret;
> > > +
> > > +		*val = (sign_extend32(reg_vals[0], 15) << 8) | (reg_vals[1] >> 8);
> > 
> > So, why the value is not marked as __be32 with the respective conversion?
> 
> regmap gives us the two 16-bit registers in native CPU endianness.

It's only if you specify endianess for the whole communication of regmap.
I'm too lazy now to check the original patch, but if it's not specified,
it means the device native endianess, whatever it is on per register basis.

> If the CPU is little endian, that means the overall 32 bits aren't in
> __be32 format (because the two bytes in each of the halves are swapped).
> 
> (Hopefully that makes sense? I'm not sure if I explained it poorly.)

But yes, even if you do it in the device native endianess, it will still be
a pair of 16-bit values with the halves being swapped in case of treating
them as a single 32-bit value. This is unfortunate... So, basically this
needs to be elaborated in the comment above (where you refer datasheet).

...

> > > +static const int fdc1004_calibbias_decomposed[] = {
> > > +	lower_32_bits(fdc1004_calibbias[0]), upper_32_bits(fdc1004_calibbias[0]),
> > > +	lower_32_bits(fdc1004_calibbias[1]), upper_32_bits(fdc1004_calibbias[1]),
> > > +	lower_32_bits(fdc1004_calibbias[2]), upper_32_bits(fdc1004_calibbias[2]),
> > > +};
> > > +
> > > +static const int fdc1004_calibscale_decomposed[] = {
> > > +	lower_32_bits(fdc1004_calibscale[0]), upper_32_bits(fdc1004_calibscale[0]),
> > > +	lower_32_bits(fdc1004_calibscale[1]), upper_32_bits(fdc1004_calibscale[1]),
> > > +	lower_32_bits(fdc1004_calibscale[2]), upper_32_bits(fdc1004_calibscale[2]),
> > > +};
> > 
> > Why do we need these tables while already having them just in different
> > format? Perhaps you can always keep the decomposed variant and otherwise
> > join them at run-time?
> 
> If we only have decomposed variants, the IIO_CHAN_INFO_CALIBBIAS
> and IIO_CHAN_INFO_CALIBSCALE branches in fdc1004_write_raw would become
> ugly and hard to read, e.g.:
> 
>     if (val64 < fdc1004_calibscale[0] || val64 > fdc1004_calibscale[2])
>         return -EINVAL;
> 
>     return regmap_write(data->regmap,
>                         FDC1004_REG_GAIN_CAL_CINn(chan->channel),
>                         DIV_ROUND_CLOSEST(val64, fdc1004_calibscale[1]));
> 
> versus

What I meant is to compare decomposed val64 as well.

>     if (val64 < iio_val_s64_compose(fdc1004_calibscale[0], fdc1004_calibscale[1]) ||
>         val64 > iio_val_s64_compose(fdc1004_calibscale[4], fdc1004_calibscale[5]))
>         return -EINVAL;
> 
>     return regmap_write(data->regmap, FDC1004_REG_GAIN_CAL_CINn(chan->channel),
>                         DIV_ROUND_CLOSEST(val64,
>                                           iio_val_s64_compose(fdc1004_calibscale[2],
>                                                               fdc1004_calibscale[3])));

You also need to make decomposed arrays to be double dimension arrays.
Otherwise this [2]/[3] is confusing in comparison to [1][0]/[1][1].

-- 
With Best Regards,
Andy Shevchenko



  reply	other threads:[~2026-10-26  9:43 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-25  5:48 [PATCH v2 0/3] " Victor Chernyakin
2026-10-25  5:48 ` [PATCH v2 1/3] iio: add IIO_VAL_DECIMAL64_{ATTO,ZEPTO,YOCTO} formats Victor Chernyakin
2026-10-25 19:41   ` Andy Shevchenko
2026-10-25  5:48 ` [PATCH v2 2/3] dt-bindings: iio: cdc: add Texas Instruments FDC1004 Victor Chernyakin
2026-10-26 13:04   ` Krzysztof Kozlowski
2026-10-25  5:48 ` [PATCH v2 3/3] iio: cdc: add Texas Instruments FDC1004 driver Victor Chernyakin
2026-10-25 21:24   ` Andy Shevchenko
2026-10-25 20:47 ` [PATCH v2 0/3] " Andy Shevchenko
2026-10-25 21:35   ` Victor Chernyakin
2026-10-26  9:35     ` Andy Shevchenko
2026-10-26 16:57       ` Victor Chernyakin
2026-10-25 22:26   ` [PATCH v2 3/3] " Victor Chernyakin
2026-10-26  9:43     ` Andy Shevchenko [this message]
2026-10-26 17:06       ` Victor Chernyakin
2026-10-26 19:48         ` Andy Shevchenko
2026-10-25 22:39 ` [PATCH v2 0/3] " Jonathan Cameron

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