From: Frank Li <Frank.li@oss.nxp.com>
To: Diogo Ivo <diogo.ivo.sx@renesas.com>
Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>,
Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Frank Li <Frank.Li@nxp.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Linus Walleij <linusw@kernel.org>,
linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org
Subject: Re: [PATCH 4/8] i3c: renesas: Add RZ/G3L support
Date: Tue, 20 Oct 2026 15:29:49 -0400 [thread overview]
Message-ID: <atfBLapPan0ucANt@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20261020-divo-ssgrlpcsrc-2966-i3c-v1-4-30a47f25e515@renesas.com>
On Tue, Oct 20, 2026 at 10:14:58AM +0100, Diogo Ivo wrote:
> Add support for the I3C Bus Interface on the Renesas RZ/G3L (R9A08G046)
Needn't "Bus Interface",
> SoC by adding the renesas,r9a08g046-i3c compatible to the OF match
> table.
>
> The controller is very similar to the IP on the RZ/G3S. However, for
> instance the RZ/G3L variant has no HDR Exit Pattern detection interrupt:
> RZ/G3S exposes 17 interrupts, while RZ/G3L exposes 16.
> A RZ/G3L node
> therefore cannot be described with the RZ/G3S compatible, as its bindings
> require at least 17 interrupts. The same point applies to RZ/G3E,
cut this part
> requires 3 clocks while the RZ/G3L requires 2.
RZ/G3S require 3 clocks while the RZ/G3L requires 2.
>
> >From the driver point of view there is no difference between the two
remove ">"
> SoCs: the driver only consumes the tclk clock, the presetn and tresetn
> resets and seven named interrupts (resp, rx, tx, st, sp, tend, nack),
> all of which are among the 16 shared ones. No driver changes are needed
> besides the new compatible.
>
> Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
> ---
> drivers/i3c/master/renesas-i3c.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c
> index 4fddc1b4fdbb..80a6df1151bf 100644
> --- a/drivers/i3c/master/renesas-i3c.c
> +++ b/drivers/i3c/master/renesas-i3c.c
> @@ -1625,6 +1625,7 @@ static const struct dev_pm_ops renesas_i3c_pm_ops = {
>
> static const struct of_device_id renesas_i3c_of_ids[] = {
> { .compatible = "renesas,r9a08g045-i3c" },
> + { .compatible = "renesas,r9a08g046-i3c" },
if there are no other difference in driver code, it is compatible with
renesas,r9a08g045-i3c,
you should change binding allow fallback to renesas,r9a08g045-i3c.
comaptible = "renesas,r9a08g046-i3c", "renesas,r9a08g045-i3c".
Frank
> { .compatible = "renesas,r9a09g047-i3c" },
> { /* sentinel */ }
> };
>
> --
> 2.56.0
>
next prev parent reply other threads:[~2026-10-20 19:30 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-20 9:14 [PATCH 0/8] " Diogo Ivo
2026-10-20 9:14 ` [PATCH 1/8] i3c: renesas: Fix zero I2C SCL rate on pure I3C buses Diogo Ivo
2026-10-20 9:27 ` Geert Uytterhoeven
2026-10-20 14:13 ` Diogo Ivo
2026-10-20 9:14 ` [PATCH 2/8] i3c: renesas: Drop comma after OF match table sentinel Diogo Ivo
2026-10-20 19:20 ` Frank Li
2026-10-20 9:14 ` [PATCH 3/8] dt-bindings: i3c: renesas,i3c: Add RZ/G3L support Diogo Ivo
2026-10-20 19:23 ` Frank Li
2026-10-20 9:14 ` [PATCH 4/8] i3c: renesas: " Diogo Ivo
2026-10-20 19:29 ` Frank Li [this message]
2026-10-20 9:14 ` [PATCH 5/8] clk: renesas: r9a08g046: Add I3C clocks and resets Diogo Ivo
2026-10-20 9:15 ` [PATCH 6/8] pinctrl: renesas: rzg2l: Split SoC-specific masks in struct rzg2l_register_masks Diogo Ivo
2026-10-20 9:15 ` [PATCH 7/8] pinctrl: renesas: rzg2l: Add RZ/G3L support for selecting I3C power source Diogo Ivo
2026-10-20 9:15 ` [PATCH 8/8] arm64: dts: renesas: r9a08g046: Add I3C support Diogo Ivo
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