Re: [PATCH v2 10/10] PCI: tegra194: Reject zero MSI interrupt number

[Frank Li <Frank.li@oss.nxp.com>]

On Wed, Oct 21, 2026 at 11:43:49AM +0530, Manikanta Maddireddy wrote:
> Reject interrupt number zero before computing BIT(irq - 1). The endpoint
> IRQ API uses interrupt numbers in the range 1-N, and existing EPF drivers
> already follow that convention. This is defensive validation rather than
> a correction to the MSI numbering used by those drivers.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> Changes V1 -> V2:
> - Retain only MSI interrupt-number-zero validation from v1 patch 10.
> - Rewrite the title and commit message around defensive MSI validation,
>   and remove the Fixes tag.
>
>  drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 632ecab3c8ea..0f49ea6df8bc 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -2026,7 +2026,7 @@ static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
>
>  static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
>  {
> -	if (unlikely(irq > 32))
> +	if (unlikely(!irq || irq > 32))
>  		return -EINVAL;
>
>  	appl_writel(pcie, BIT(irq - 1), APPL_MSI_CTRL_1);
> --
> 2.34.1
>