From: Drew Fustini <fustini@kernel.org>
To: Zeng Heng <zengheng@picoheart.com>
Cc: "Adrien Ricciardi" <aricciardi@baylibre.com>,
"Alexandre Ghiti" <alex@ghiti.fr>,
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Subject: Re: [PATCH v10 2/6] riscv_cbqri: resctrl: Add cache allocation via capacity block mask
Date: Fri, 6 Nov 2026 09:05:32 -0800 [thread overview]
Message-ID: <au4I3E_qcPhIr-Qr@thelio> (raw)
In-Reply-To: <02cf71f0-09d5-4dde-a8cf-3739583cc7fa@picoheart.com>
On Thu, Nov 05, 2026 at 04:05:29PM +0800, Zeng Heng wrote:
> Hi Drew,
Hi, thanks for reviewing.
> 在 11/5/26 上午12:35, Drew Fustini 写道:
>
> ...
>
> > +/*
> > + * Fill the rdt_resource fields for one picked rid. An rid with no picked
> > + * controller is left untouched so it stays out of resctrl_arch_get_resource().
> > + */
> > +static void cbqri_resctrl_control_init(struct cbqri_resctrl_res *cbqri_res)
> > +{
> > + struct rdt_resource *res = &cbqri_res->resctrl_res;
> > + struct cbqri_controller *ctrl;
> > +
> > + if (!cbqri_res->nr_ctrls)
> > + return;
> > + ctrl = cbqri_res->ctrls[0];
> > +
> > + switch (res->rid) {
> > + case RDT_RESOURCE_L2:
> > + case RDT_RESOURCE_L3:
> > + res->name = (res->rid == RDT_RESOURCE_L2) ? "L2" : "L3";
> > + res->schema_fmt = RESCTRL_SCHEMA_BITMAP;
> > + res->ctrl_scope = (res->rid == RDT_RESOURCE_L2) ?
> > + RESCTRL_L2_CACHE : RESCTRL_L3_CACHE;
> > + res->cache.cbm_len = ctrl->cc.ncblks;
> > + res->cache.shareable_bits = 0;
> > + res->cache.min_cbm_bits = 1;
> > + res->cache.arch_has_sparse_bitmasks = false;
>
> Currently, the driver sets arch_has_sparse_bitmasks to false, causing
> resctrl to require a contiguous bits in cache allocation masks. For
> example, L3:0=3 is accepted, whereas L3:0=11 is rejected because its
> set bits are non-contiguous.
>
> The default should allow both contiguous and non-contiguous masks,
> provided they satisfy the other mask validity checks. A contiguity
> restriction should only be imposed when a specific hardware
> implementation can't support sparse masks explicitly.
>
> So I propose enabling sparse cache allocation bitmasks by default.
> Thanks.
Good point, I will change arch_has_sparse_bitmasks to true. The spec
defines cc_block_mask as one bit per capacity block and there's no
contiguity requirement.
> > + res->cdp_capable = ctrl->cc.supports_alloc_at_code;
> > + res->alloc_capable = ctrl->alloc_capable;
> > + INIT_LIST_HEAD(&res->ctrl_domains);
> > + INIT_LIST_HEAD(&res->mon_domains);
> > + break;
> > + default:
> > + break;
> > + }
> > +}
>
> Apart from this,
>
> Reviewed-by: Zeng Heng <zengheng@picoheart.com>
Thanks!
Drew
next prev parent reply other threads:[~2026-11-06 17:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-04 16:35 [PATCH v10 0/6] riscv: Add initial CBQRI resctrl support Drew Fustini
2026-11-04 16:35 ` [PATCH v10 1/6] riscv_cbqri: Add capacity controller core Drew Fustini
2026-11-04 16:35 ` [PATCH v10 2/6] riscv_cbqri: resctrl: Add cache allocation via capacity block mask Drew Fustini
2026-11-05 8:05 ` Zeng Heng
2026-11-06 17:05 ` Drew Fustini [this message]
2026-11-04 16:35 ` [PATCH v10 3/6] riscv_cbqri: Make RESCTRL_FS available on RISC-V Drew Fustini
2026-11-04 16:35 ` [PATCH v10 4/6] dt-bindings: riscv: Add binding for CBQRI controllers Drew Fustini
2026-11-04 16:35 ` [PATCH v10 5/6] riscv_cbqri: Add CBQRI capacity allocation platform driver Drew Fustini
2026-11-04 16:35 ` [PATCH v10 6/6] MAINTAINERS: resctrl: Add myself as reviewer Drew Fustini
2026-11-04 17:05 ` Reinette Chatre
2026-11-05 1:14 ` [tip: x86/urgent] " tip-bot2 for Drew Fustini
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