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From: Chen Yu <yu.c.chen@intel.com>
To: Reinette Chatre <reinette.chatre@intel.com>, <tony.luck@intel.com>
Cc: "Luck, Tony" <tony.luck@intel.com>,
	Fenghua Yu <fenghuay@nvidia.com>,
	Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>,
	Peter Newman <peternewman@google.com>,
	James Morse <james.morse@arm.com>,
	Babu Moger <babu.moger@amd.com>,
	Drew Fustini <dfustini@baylibre.com>,
	Dave Martin <Dave.Martin@arm.com>, <x86@kernel.org>,
	<linux-kernel@vger.kernel.org>, <patches@lists.linux.dev>
Subject: Re: [RFC PATCH 0/8] arm,x86,fs/resctrl: Support asymmetric L2 cache allocation
Date: Wed, 4 Nov 2026 00:31:46 +0800	[thread overview]
Message-ID: <auoMcjGLGnwiynCX@chenyu-dev> (raw)
In-Reply-To: <dbc8fc24-2ca3-4152-9bfa-81b6e5d502a9@intel.com>

On Tue, Oct 27, 2026 at 11:30:37AM -0700, Reinette Chatre wrote:
> Hi Tony,
> 
> > # tree
> > .
> > ├── cpus
> > ├── cpus_list
> > ├── info
> > │   ├── L2
> > │   │   ├── bit_usage
> > │   │   ├── control_mode
> > │   │   ├── min_cbm_bits
> > │   │   ├── num_closids
> > │   │   ├── schemata
> 
> This needs an L2 control. As I highlighted in 
> 
> 	https://lore.kernel.org/lkml/22ecec13-a703-414e-9f5e-75c89173e845@intel.com/
> 
> when considering pqos utility user space expects an L2 schemata file entry
> when there is an L2 resource.
> 
> Since L2_ASYM is the native interface it could be used to emulate the legacy L2 control
> albeit with poor performance. By default the schemata file only contains the L2 control
> and a user space familiar with new interface can enable L2_ASYM to replace L2 control
> in schemata file.
>

In current patch it seems that we did not create any new controller, and fixes the
per rdt_ctrl_domain's cbm_len, I'm trying to understand why do we need to create a new "native"
controller?

Anyway, if we introduce a new controller, and keep the legacy interfaces, we might want to
encourage the user to switch to the new ones, would the following proposal be doable?

1.When booting up with control_mode = legacy, and the new control mode is supported
(asymmetric, region-aware, etc.), we can print a message saying: new control is available,
please switch the control_mode to "native".

2.Add a mount option to support control_mode.

3.The rdt= option, but only for x86 — not sure why rdt= is not a generic option.

thanks,
Chenyu

      reply	other threads:[~2026-11-03 16:43 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-26 21:57 Tony Luck
2026-10-26 21:57 ` [RFC PATCH 1/8] fs/resctrl: Change UI of "max" file (merge back into earlier patches) Tony Luck
2026-10-26 21:57 ` [RFC PATCH 2/8] x86/resctrl: Add L2CAT quirk for Intel Panther Lake Tony Luck
2026-10-26 21:57 ` [RFC PATCH 3/8] x86/cpuid: Add and use defines for Intel RDT enumeration leaves Tony Luck
2026-10-26 21:57 ` [RFC PATCH 4/8] x86/resctrl: Add X86_FEATURE bits for asymmetric L2 Tony Luck
2026-10-26 21:57 ` [RFC PATCH 5/8] x86/resctrl: Refactor rdt_get_cache_alloc_cfg() Tony Luck
2026-10-26 21:57 ` [RFC PATCH 6/8] arm,x86,fs/resctrl: Prepare for asymmetric caches Tony Luck
2026-11-03 15:31   ` Chen Yu
2026-11-03 18:23     ` Luck, Tony
2026-10-26 21:57 ` [RFC PATCH 7/8] x86/resctrl: Check for and enable asymmetric L2 cache allocation Tony Luck
2026-10-26 21:57 ` [RFC PATCH 8/8] fs/resctrl: Suppress creation of cbm_mask info file on asymmetric systems Tony Luck
2026-10-26 22:30 ` [RFC PATCH 0/8] arm,x86,fs/resctrl: Support asymmetric L2 cache allocation Reinette Chatre
2026-10-27 17:41   ` Luck, Tony
2026-10-27 18:30     ` Reinette Chatre
2026-11-03 16:31       ` Chen Yu [this message]

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