Re: [PATCH v7 12/12] serial: 8250_dw: configure RX trigger thresholds for Octeon

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

On Tue, Nov 03, 2026 at 02:40:05PM -0700, James Hilliard wrote:
> Octeon uses the DesignWare receive-trigger mapping with a 64-byte FIFO,
> giving thresholds of 1, 16, 32 and 62 bytes. Its setup bypasses
> dw8250_setup_port(), so it does not install the common trigger callbacks.
> PORT_OCTEON also has no static trigger table, so rx_trig_bytes is not
> exposed.
> 
> Supply the fixed depth from platform data when firmware has not provided
> one and initialize the common trigger table before port registration.
> This makes rx_trig_bytes available while preserving the Octeon port type
> and register accessors.
> 
> Select DMA before filling in the default depth, as before when the 8250
> core supplied that default during registration. Thus the new trigger
> setup preserves which ports attach DMA and their existing burst sizes.

...

> +	if (!p->fifosize)
> +		p->fifosize = data->pdata->fifo_size;

In this case I would use ternary Elvis:

	p->fifosize = p->fifosize ?: data->pdata->fifo_size;

-- 
With Best Regards,
Andy Shevchenko